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In case of timing diagrams of 8085, what I saw is that, always Opcode Fetch, Memory Read/Write, IO Read/Write is shown but execution is never shown. Is it because the execution time is too less compared to others? Thanks in advance.
For example, In case of MVI A, 55H they show 4 T state for Opcode Fetch, 3 for M/m Read that's it. No T state for execution is ever shown.
Reference: Ramesh Gaonkar 8085 Microprocessor Book.
In the history of microprocessors the start was with very slow processors and very fast memory (a 6502 did a fetch, then execute, and in the execute phase the memory was free to be used for other purpsoes, like DMA or video generation). The Z80 had similar 'idle' period in the instruction execute that could be sued for DRAM refresh.
With the generation of the 8085 the controller could just about finish an instruction before the memory was ready for the next memory cycle, hence the execution time does not show in the timing graphs.
After this the situation got more confused. On the one hand the controllers got faster, so the bus timing became totally dominated by memory access. But on the other hand controllers started to implement much more complex instructions like multiply and divide, which do show up in the timing. And the addition of caches and pipelining make everying even more confused.
Probably such timing is not shown because it is irrelevant to using the processor. All you need to know is that the result of one instruction is available as input to the next, except when it is stated to the contrary. Where exactly in the cycle the operation takes place or finishes is irrelevant because there is nothing you can do about it whether it finishes halfway thru or just before the end. At the maximum instruction clock, the most complicated operation probably finishes just before the end of the instruction, with whatever margin is necessary to guarantee correct operation over all the operating conditions.
