FPGA Simulation - VHDL Testbench

Question

I've been designing a FPGA board that will become a single node of many in a computation cluster I am building for some scientific computing. The hope is to make it scale-able and allow me to update it to expand into further forms of computation (security, simulations, etc.).

Essentially I have been using development boards to simulate and test GPIO and USB, Ethernet and the like. However, my implementation currently uses 4 FPGAs, and I intend to increase that number and my budget simply does not support buying multiple development boards to test moving job data between the FPGAs.

I essentially need to simulate my environment, and even though I have plenty of computational ability (I have an entire lab at my disposal), I am currently trying to develop a test bench for moving data between the FPGAs as well as a DDR3 memory controller that I intend to implement for large data movement and manipulation.

Since most of my work with FPGAs has allowed me to avoid the use of a test bench, I have yet to develop one in order to verify my simulated results. All of which is done on Xilinx thusfar.

Any ideas on where I may start with developing a VHDL test bench?

Answer 1

It all depends on what you want to simulate.

It is pretty easy to create a test bench to create a clock, set up a few IOs etc, but it gets much more complicated if you want to simulate USB or other protocols.

This web page will give you a pretty good overall understanding on how to do this:

FPGA programming step by step

There are some commercial tools to help you with creation of TBs, but there are also free tools such as "The VHDL Test Bench" to help you creating the TB faster and easier.

For a large project like yours (I assume it is large since you have 4 FPGAs in your design and lots of IPs), I would suggest you sit down and decide WHAT you want to test, what is your goal with the simulation and how much time do you want to spend on doing this. Then make a list of the blocks you want to test and either find stimuli files for them or write them yourself.

Answer 2

Testbenches are not that difficult. A starting point in reading could be the Doulos website. There you will find a short introduction in testbenches.

In short, you write them in an HDL language (VHDL, Verilog, ...). The test bench is playing the role of the world outside your design/FPGA. So it could generate some input clocks or other input signals. And could check if the output of your design is what you where expecting. Your design itself is then an instantiated block (usually called DUT, Device Under Test) in your testbench.

You compile the testbench and design with a compiler and simulate with for example Modelsim (Mentor) or Isim (Xilinx).