# Switching regulator layout advice

I am planning to use a Diodes AP5100 switching regulator to go from ~22V to 12V in my circuit, which will have a max current draw of about 1A. This is my first attempt at laying out a switching power supply and I tried to follow the recommendations (double quoted below) in the datasheet as closely as possible.

"The input capacitor needs to be as close as possible to the IN and GND pins."

• I put C1 close to IN pin 5. Should I try to get C1 closer to the ground pin 2?

"The external feedback resistors should be placed next to the FB pin."

• R1 & R2 feedback resistors are near FB pin 3. I could move it closer if needed.

"These interconnecting impedances should be minimized by using wide, short printed circuit traces."

• I believe that was accomplished.

I am not sure if it's a good idea to route R2's ground connection under the IC to ground pin 2? Maybe using a via directly to the ground plane is better?

Also, I am not sure if the ground island for minimizing ground bounce is laid out correctly or is even is necessary. It actually might be makings things worse in terms of EMI.

I think the inductor that I am planning to use might be too small. It's current rating is only 1.6A.

Please offer any advice on how to improve the layout or anything else.

Revision #2

Thanks to everybody for all of the suggestions and I made the following changes:

• removed the ground island
• moved L1 closer to pin 6
• feedback measured directly off C2 now
• added double vias to the ground plane for C1, D1 and C2
• added a second GND connection

Questions:

• should pin2's ground connection be made with a double via also?
• A minor suggestion: Consider having two ground (GND) pads instead of just one. This simplifies connecting a pair of connectors each to the input (IN & GND1) and output (OUT & GND2). Your ground plane has sufficient space to permit the additional ground connection. Jul 11 '13 at 5:52
• Definitely the ground island doesn't help in this design. My suggestions: add a second GND pin as @Anindo said. Check the placement for L1 (bit closer to D1 and IC1). The voltage you want to measure as feedback is the voltage in C2. So route the track from it. Anyway, good first approach! Jul 11 '13 at 10:13
• @JesúsCastañé I agree, this is a great first approach. Jul 11 '13 at 10:21
• @user26200 After the update. The second layout looks fine. I think you can connect pin2 with two vias. You will get a lower inductance in that connection. Jul 12 '13 at 11:03

General Information and Current Flow

Buck converter has two stages depending on the state of the switch. The switch, in your case, is in the IC and is in between pins 5 and 6. Let's draw the first stage where the switch is ON and D1 is reverse biased. As you can see, the loop is big, because the ground island limits where the current can flow. In order to have a smaller loop, it should have returned right under the yellow trace.

In the other stage, which is not drawn here, things are almost going to be the same, because of the ground island.

Here is a good read on ground bounce.

Also, here is a very good read on SMPS layout which includes a section in page 14, about laying out feedback resistors. According to it, instead of connecting C6-R1 junction to L1's pin, connect them to C2's pin. This will reduce the amount of extra current that this track will carry.

Your inductor is fine if it does not saturate at 1.3 A which is stated in the datasheet as below. So, a 1.6 A rated inductor will do fine. Increasing the inductance to 10uH may improve your light load efficiency, but if it brings a higher DC resistance, than you will have lower rated-load efficiency.

Choose the inductor ripple current to be 30% of the maximum load current. The maximum inductor peak current is calculated from:

$I_{L_{MAX}}=I_{LOAD}+\dfrac{\Delta I_{L}}{2}$

A 1µH to 10µH inductor with a DC current rating of at least 25% percent higher than the maximum load current is recommended for most applications.

What to do?

What I would recommend is to remove that island completely and have a solid unbroken ground plane. Also, adding multiple vias right near every grounded pin, for example right near C2's pin on the right side.

One more thing to say is that your input capacitor C1 may not be enough. I once made a buck converter with a TPS5450 chip which also, in the datasheet, recommended a 10 uF input capacitor. After couple of fried chips, it turned out 10uF was not enough. I would recommend adding 2 more footprints so that you can populate a 22uF and a 100nF, later on, if needed.

• I disagree about your interpretation of the document in your link. The ground end of R2 MUST return directly to the ground pin on the chip (pin 2). If the ground track to C2 has IoR drop, this will become superimposed on the FB pin and this is not desirable. Jul 11 '13 at 9:49
• You are right about the "reference" statement. I have edited that part out of my answer. Jul 11 '13 at 9:56

C1, D1 and C2 (and L1)

C1, D1 and C2 carry big currents to ground and, as a priority, MUST make their ground connection right back to pin 2 of this device. No options on this if you want it to work with low ripple. Think of pin 2 a star-point. These ground connections should join at pin 2 ideally and not (for instance) join at some point and have a common track to pin 2.

D1 connection to pin 6 OK. C1 connection to pin 5 OK. C2 connection to L1 OK but L1 connection to pin6 can be shorter.

Other stuff

R2 tracking is correctly routed - straight back to pin 2 on the ground side - do not let this track carry any currents other than R2's.

I wouldn't bother with the ground plane idea you have - just follow what I've said and have a full ground plane.

• Actually, with this layout, there are some more current than R2's that the feedback ground track carry. Jul 11 '13 at 7:41
• @abdullahkahraman I don't understand what you are implying. R2 ground connection MUST go back to pin2 and it MUST do so without making a significant connection to other ground ground points. Jul 11 '13 at 8:37
• Check out Pg. 13 and 14 of this application note. Since feedback pin (pin 3) of the IC is very high impedance relative to the feedback resistors, where the current flows, the IC's ground is not important in terms of current flow.So, R2 ground connection should better go to output capacitor's ground connection via a lonely trace. I am no expert, in fact I am a newbie on electronics, but this is what I understand from this App-Note. Jul 11 '13 at 9:25
• @abdullahkahraman I think you misinterpret 5(c) with what I'm saying - it implies that the "collection" of feedback will also "collect" IoR volt drops. I'm not advocating this - I'm advocating a star-point at pin 2 so in effect where R2 connects to the output cap in 5(d) that is the star point. The feedback amp inside this chip (and I would say all switchers with single-ended FB measurement) makes an internal reference to the voltage on pin2 and that is therefore where r2 should directly return and so should the output capacitor. Jul 11 '13 at 9:46
• Oh, OK, I see. What I was missing was the "reference point". Thanks for pointing this out. Jul 11 '13 at 9:55