Designing a latch with no constant power supply

Question

I am trying to design a latch for an energy harvesting application with a very low power system. Basically I have a setup with a 3.3V regulated output driving a circuit, which is run off a capacitor being charged by an energy harvesting system. If the system ever turns off because it runs out of energy, I want a switch to prevent any current from flowing from the 3.3V output to the circuit. This turning off can be detected by the output falling below 3.3V or from the charge across the capacitor dropping below 4V. I then dont want to close the switch again until the capacitor is charged up to 16V, at which point the system should start drawing power. Something that may be useful is that the output will always be at 3.3V when the capacitor is charged to this level.

I am having trouble with this because there is no true constant voltage supply and the system needs to be low power. I also may need the system to stay on for long periods of time once the switch closes.

Some form of comparator with hysteresis of a few volts could work? but I do not know how I would get this to happen without some Vcc input.

As an update, I attempted to use a comparator tied to a latch that I thought would stay on until there was no power to it, but it does not seem to have worked. any advice on getting this to stay on until it dies? https://www.circuitlab.com/circuit/67e536/possible-latch-mide/

Answer 1

While a well-balanced back-to-back pair of inverters is powered on, it will have a strong tendency to drive itself toward one of two states; by "overpowering" one of the inverters, it's possible to switch it to the other state. If power is removed, internal node capacitance will cause its internal circuit nodes to hold a significant portion of their charge for quite some time; re-applying power will cause the device to power back up in its previous state. If the circuit is powered off for a long time, it's possible that enough charge may dissipate that the next power-on cycle will be in the wrong state, but that may take many minutes or even hours.

If the circuit is perfectly balanced, the power-on state after a long time being powered off may be unpredictable. If one unbalances the circuit slightly, one can ensure that the circuit will "drift" toward one state or the other, at the expense of reducing the amount of time the circuit can "remember" the other state. Note also that it's important to ensure that the circuit is free from disturbance while the remainder of the circuit is powered on and off. That's the reason for using inverters rather than the more "usual" NAND or NOR gates.

If one uses two inverters, fed back to each other through resistors, and then has N-channel MOSFETs which can pull either inverter's input low, then provided that outside circuitry does not put positive voltage on the gates of those MOSFETs, the latching circuit will be free from outside influence. If the inverters are on a chip by themselves, it is diode-isolated from the system's main power supply, and there are capacitors from each inverter input to ground, it may be possible to extend the "memory" time to days or weeks, though I've not tried such a thing.