# Limiting the input current with voltage divider

I would like to measure two signals with a microcontroller ADC:

• 0 to 5V, 5MHz
• -36 to +36V 100Hz simulate this circuit – Schematic created using CircuitLab

I want to draw as small current as possible from the input signal. I chosed the OPA365 amplifier to shift the signal and provide the current for the ADC.

• My first question is how I should choose the resistors?
• How can I change the value of the R15?

I don't have a DAC on the MCU, but I have GPIO, I thought I can connect TS12A4517 to switch between different resistor values. Is it a good idea? simulate this circuit

• Do you mean a voltage shifter? – The Photon Jul 13 '13 at 20:21
• Yes, the autocorrect has changed the word – OHLÁLÁ Jul 13 '13 at 20:25
• You have shown the signal in your diagram as a floating voltage source. I have doubts that this is the case so please tell more about the signal you are trying to measure. Is it to be fed into an ADC on the micro/MCU? By the way, the circuit you have drawn would still destroy the op-amp I believe so to help you, you have to disclose more info about the source voltage and what it connects to. – Andy aka Jul 13 '13 at 20:57
• No, it's not a floating voltage source, I am new with the circuit lab. Actually I have to signals, one between -5,5 and one between -15,15, on the MCU I don't have a DAC to I would like to use TS3A4751 analog switch to change the R15 value. – OHLÁLÁ Jul 13 '13 at 21:50
• I revised my question and the schematic. Thanks for your help. – OHLÁLÁ Jul 14 '13 at 15:09

## 3 Answers

Given the spread of voltages and frequencies that you need to measure I would firstly concentrate on the 100Hz signal - say you attenuate it by 30 - this would take it from 72Vp-p to 2.4Vp-p and to keep the impedances low I would use a capacitive divider formed by a 10pF capacitor and a 290pf capacitor.

Given also that you maybe be interested in the dc levels (you will be for the 5MHz signal) I would add resistors across the 10pF and 290pF that have the same ratio of impedance say 1Mohm across the 10pF and 34.5kohm across the 290pF.

Next is the problem of the 5MHz signal and you need to attenuate this by (say) 2:1 - this means the 34k5 and 290pF need to be replaced with (say) another set of 10pF // 1Mohm. I would then consider that these extra components were permanently in-circuit and that the 290pF and 34k5 were in fact 280pF // 35k7 so that when in parallel with 10pF // 1Mohm gave 290pF // 34k5.

I would consider use a low capacitance JFET for the switching: - Also shown is the OPA354 which is a low input capacitance, unity-gain-to-40MHz op-amp with decent offset voltage, bias currents and noise. It is typically run from a split supply of +/-2.5V centred on 0V. The supply is split like this to accommodate the 100Hz AC signal but it gives a tiny problem for the 5MHz signal because, with the attenuation of 2:1 at 5MHz the input would equal the power rail - this means the attenuation should be designed to be a tad lower at maybe 2.5:1. These values can be easily calculated from the ones shown i.e. the lower 1Mohm becomes 667k and the lower 10pF becomes 15pF. These changes will have a small knock-on effect on the 35k7 and 280pF.

I would also consider the 15pF cap becoming a trimmer to get the peaking just right - setup would be just like on an oscilloscope probe when trimming. JFET - 2N3819 should work ok - it has a drain capacitance of about 1pF.

Why take this approach? To work effectively across the voltage and frequency range needed if only resistors were used, it is likely that input capacitance on op-amps and switching circuits (like JFETs or analogue switches) would make a bit of a mess of things. With "same ratio" capacitors these effects are reduced. More to follow as I think a little more about this.

• During the weekend I work on this a bit, here is my solution: circuitlab.com/circuit/gy23wm/screenshot/1024x768 the c1,c2 will be variable capacitor. I though I can use a solid state relay(like this clare.com/home/PDFs.nsf/www/Lcc110.pdf/\$File/Lcc110.pdf) to switch between the two input. – OHLÁLÁ Jul 22 '13 at 7:34
• @run - similar solution - finding an amp that doesn't have too much input capacitance is the next stage. – Andy aka Jul 22 '13 at 8:11
• I already found one: ti.com/lit/ds/symlink/opa2354.pdf On the 14th page there is an exmple to feed the ADC. What I don't understand why is it there a 330pF capacitor? What is the purpose of that? In this configuration that is a filer. Am I right? – OHLÁLÁ Jul 22 '13 at 9:41
• @run The 330pF is because the ADC shown is only 200ksamples per sec and the cap does some anti-alias filtering at 96kHz. You don't need the cap but also you don't need an inverting amplifier either. I was looking at AD8033 but i'll redo my diagram with the opa2354 – Andy aka Jul 22 '13 at 9:55

If your goal is to minimize the current drawn from your signal source, then what you are looking for is a voltage buffer.

Also, you haven't said, but from the +3.3 V supplies scattered around your schematic, I'll assume your ADC has an input range of 0 to +3.3 V.

For your first case, with input signal between 0 and 5 V at 5 MHz, the best way to minimize the input current of your circuit is to place the buffer amplifier first, and then use a resistor divider to adjust the voltage range. simulate this circuit – Schematic created using CircuitLab

How to choose the resistors? If the resistor values are too high, then the current in to the ADC input will change the voltage at the "TO ADC" node, causing an error in the reading. If the resistor values are too low, then the op-amp will have to supply a large current, and its distortion will increase. You'll have to work out the balance between these two issues, given the ADC you've chosen and the accuracy you need.

If you find that even the highest resistor values that work with your ADC are causing a distortion problem with your op-amp, you could add a second buffer stage after the resistor divider.

For your second case, a +/- 36 V signal at 100 Hz, you have a more difficult problem. To use the same circuit from above, you'd need an op-amp running on probably +/- 40 V supplies (because high-voltage op-amps aren't likely to rail-to-rail inputs). Which would probably mean adding +/-40 V supplies to your system.

The simplest way to deal with this, assuming your input signal has near 50% duty cycle, is probably by ac-coupling: simulate this circuit

So in this case, how do we choose the resistors?

Once again, we need the resistors low enough that the current going to the next stage doesn't disturb the voltage divider. If you're using the OPA365, that input current is on the order of 10 pA. Given the values I drew above, this current will cause about 1 uV change in the voltage at voltage divider node. Since this is well below the 100 uV offset voltage of the OPA365, it won't be a noticeable error contributor in your circuit.

And again, you need to increase the resistors to minimize the load on the source. In this case the input current will be 36 V / 2 MOhm, or about 18 uA. If this is too high for your source, you'll want to scale up the resistor values, or find a way to buffer the source before scaling it.

Another thing to watch out for with these large resistor values is whether our circuit will restrict the bandwidth of the signal too much. Our divider has an equivalent output resistance of about 90 kOhms, and it's feeding an op-amp with about 6 pF input capacitance (again, considering the OPA365). This gives a time constant of 270 ns, or a cut-off frequency of 600 kHz. If this had come out below our signal frequency (100 Hz), we'd need to look in to scaling down the resistor values, or finding an op-amp with lower input capacitance.

• Thanks for your advice, I have only one ADC channel, so I have to use the same circuit with some switch. – OHLÁLÁ Jul 14 '13 at 17:28
• You can have the switch after the buffer stages. – The Photon Jul 14 '13 at 17:37
• Whit my schematic is not possible to measure the two signals, by switching different R14 resistor values? In this case would be possible to measure different signals with different voltage levels. The zener diode will provide over voltage protection. Is my solution not really recommendable? – OHLÁLÁ Jul 14 '13 at 17:52
• As drawn, your circuit will, when the input voltage is positive, try to make a negative output voltage. But it won't be able to because you have only a +5 and 0 V supply. – The Photon Jul 14 '13 at 18:06
• this is why I have a voltage shifter, With the voltage divider I can dived the +/-36V to +/-1.5V and shift to 0-3V by using the amplifier. – OHLÁLÁ Jul 14 '13 at 19:05

It's worthwhile to note that many ADC's will perform poorly unless either the RC time constant formed by the effective input resistance and the sum of the sampling cap and all parasitic capacitance is not much smaller (at least an order of magnitude) than the acquisition time of the ADC, or else the capacitance on the pin is many orders of magnitude larger than the sampling cap on the ADC. Effectively, what happens is that just before taking a reading, the ADC connects the input to a sampling cap which has been charged so some arbitrary voltage [on some ADCs, the voltage will generally be something close to the last value read; on some it will be zero; on some it will arbitrarily be high or low with no discernible pattern]. If the RC time constant is small, the pin will "rebound" to the correct voltage quickly enough to allow an accurate measurement. If the capacitance on the pin is large enough, connecting the small cap won't budge it. If neither condition applies, however, the cap will disturb the input voltage enough to be measurable, and this disturbance will last long enough to corrupt the measurement.

While I can't offer recommendations with regard to particular op amps, I should note that some low-power op amps will allow their output to move quite a bit when the ADC connects its sampling cap, and will be rather slow to move the pin back to its correct level. If you can afford it, I would suggest having the op amp drive a fairly large cap, so that the cap can keep the pin from moving very much before the op amp has a chance to react.

• "I would suggest having the op amp drive a fairly large cap", but also remember that you will have to be careful of the stability of the op-amp circuit when it drives a capacitive load. – The Photon Jul 16 '13 at 19:03
• @ThePhoton: That is true, though I expect "middle-value" caps are more likely to be a problem than big ones. Of course, it's possible that a cap sized just large enough to avoid disruption by the ADC could be a really horrible value for the op amp: too big to settle quickly, but not big enough to limit the amplitude of oscillations. – supercat Jul 16 '13 at 19:11