# Ideal D Flip Flop

When assuming that an D Flip Flop is ideal, which of the situations are possible?

• While testing a circuit, the signal Q is observed changing as frequently as the signal c does.

• While testing a circuit, the signal i is observed changing more frequently than the signal c.

• While testing a circuit, the signal Q is observed changing more frequently than the signal c.

• While testing a circuit, the signal i is observed changing more frequently than the signal Q.

• While testing a circuit, the signal Q is observed changing less frequently than the signal c.

In all of these situations c is the clock, i is in the input for D, and Q is the output. My initial guess is that the last two choices are possible because Q is based off of the last change of i before the rising edge of the clock. Would my assumptions be correct?

Your answer is almost correct. The last two are indeed possible, because Q can only change when i changes, and Q changes at most half the speed of c. However, you are missing one case. As a hint, remember that i can do whatever it wants, regardless of c or Q.