# Ideal D Flip Flop

I am a little confused about this homework question:

When assuming that an D Flip Flop is ideal, which of the situations are possible?

• While testing a circuit, the signal Q is observed changing as frequently as the signal c does.

• While testing a circuit, the signal i is observed changing more frequently than the signal c.

• While testing a circuit, the signal Q is observed changing more frequently than the signal c.

• While testing a circuit, the signal i is observed changing more frequently than the signal Q.

• While testing a circuit, the signal Q is observed changing less frequently than the signal c.

In all of these situations c is the clock, i is in the input for D, and Q is the output. My initial guess is that the last two choices are possible because Q is based off of the last change of i before the rising edge of the clock. Would my assumptions be correct?

## 1 Answer

Your answer is almost correct. The last two are indeed possible, because Q can only change when i changes, and Q changes at most half the speed of c. However, you are missing one case. As a hint, remember that i can do whatever it wants, regardless of c or Q.

• Ah, alright. So choices 2, 4, and 5 would be all of the possible cases than? – Charles Witiker Jul 14 '13 at 17:28
• Yep, that's correct. – helloworld922 Jul 14 '13 at 18:56
• Thank you. Just to clarify it wouldn't be possible for Q to change as frequently as the clock, correct? – Charles Witiker Jul 14 '13 at 22:18
• Yes, because Q only changes on the rising edge. – helloworld922 Jul 14 '13 at 23:11

## protected by user3624 Sep 11 '13 at 1:15

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