Is there a way in verilog to do the following? I have a variable number of FIFOs (1 to 4) created with a generate statement inside of a module


    generate( for i to NUM_FIFOS )
        FIFO fifoI( args )

What I want to do is have the read data from these FIFOs as outputs of the entire module. Is there a way to have a variable number of output?


    generate for( i = 0 to NUM_FIFOS )
        output FIFO_dataI

Thanks for the help!


1 Answer 1


Use a parametrized bus width:

module FIFO #(WIDTH=8) (
  output [WIDTH-1:0] out,
   /* other ports */

Then overwrite the parameter when generating the instances.

module top #(NUM_FIFO=4,WIDTH_FIFO=8)(
  output [NUM_FIFO*WITDH_FIFO-1:0] FIFO_data,
   /* other ports */);
/* ... other code ... */
genvar i;
    for(i=0; i<NUM_FIFO; i++) begin : gen_fifo
        FIFO #(.WIDTH(WIDTH_FIFO)) fifoI (
          .out( FIFO_data[i*WIDTH_FIFO +: WIDTH_FIFO] ),
          /* args */ );
    end : gen_fifo
endmodule : top
  • 1
    \$\begingroup\$ This is the right answer, but its also worth noting that a define statement can be used as well. I prefer to use parameter when the constant is used in only the local file and I use define when the constant spans multiple files. But it is up to the designer's discretion. \$\endgroup\$ Jul 16, 2013 at 2:30
  • \$\begingroup\$ Thanks for the answer. Are generates synthesizable, though? \$\endgroup\$
    – ballaw
    Jul 16, 2013 at 5:39
  • \$\begingroup\$ @ballaw, generate statements are generally synthesizeable. \$\endgroup\$ Jul 16, 2013 at 7:14

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.