In general, it is possible and quite common to use back-to-back three-state buffers for bidirectional bridging. Such bridges, however, need something to tell them when they should conduct in each direction. For example, in many microprocessor systems, the processor will sit on a local data bus along with its memory, and that will be connected to a system data bus through such a bidirectional bridge consisting of back-to-back three-state buffers (the most commonly-used chips for such purpose would have 8 back-to-back pairs of 3-state drivers, but it would be possible to use chips with unidirectional 3-state drivers and wire them back to back). When the processor wants to write data to the external bus, the drivers are enabled in one direction. When it wants to read data, they are enabled in the other direction.
Such devices work very well in situations like microprocessor buses where there are pre-existing signals that specify which direction they should operate. They will not be sufficient for something like a full I2C implementation, in which the direction of of the clock wire may reverse without any transitions on it. To clarify, a data read or slave-acknowledge clock cycle on I2C behaves as follows:
- Master asserts SCK (drives it low)
- Slave sees SCK asserted, and starts driving it low as well
- Slave determines whether it should assert or release SDA (may be instantaneous, or could take hundreds of microseconds)
- Slave asserts or releases SDA as appropriate, and releases SCK
- Master sees SCK released and processes data on SDA
It is imperative that the slave's SCK wire not be released until the master decides to release it, and also that the master's SCK wire not be released until the slave decides to release it. It is not possible to accomplish this with conventional logic, since there would be no way of knowing whether either side had released SCK without releasing SCK to that side. Philips in their I2C bridging chips gets around this by using chips that process multiple logic levels. Essentially, what happens is that when the SCK wire on either side is driven "hard" low, the SCK wire on the other side will be driven low, but somewhat less strongly. Strongly enough that attached devices will see the signal as a low, but weakly enough to be distinguished from an externally-driven strong low.
Note that in scenarios involving a single master and not using clock-based handshaking, it may be possible to build an I2C bridge using only conventional logic levels, since the direction of the SDA wire would be well defined at all times, but keeping track of the I2C communication state would be sufficiently complicated that using an I2C bridge chip would probably be easier.