What is the maximum clock difference between a transmitter and receiver for error-free asynchronous serial communication?


3 Answers 3


Feel free to edit in more values. These are the ones I'm using now.

Atmel ATmega UART:

5 bits, normal speed : ±3.0%
5 bits, double speed : ±2.5%
10 bits, normal speed: ±1.5%
10 bits, double speed: ±1.0%

NXP LPC111x (Cortex-M0) UART: 1.1% (no table)

Microchip PIC 18F2XK20/4XK20: not defined. (wtf.)

As the venerable Mr. Horowitz & Hill put it:

By resynchronizing on the START and STOP bits of each character, the receiver doesn't require a highly accurate clock; it only has to be accurate and stable enough for the transmitter and receiver to stay synchronized to a fraction of a bit period of the time of one character, i.e., an accuracy of a few percent.

Note that conductor length plays a large part in serial clock errors. I stay under 19200 baud for regular ribbon cable more than 2' long. Makes me jealous of 4' 60Gb/s USB lines.

  • \$\begingroup\$ Where did you get these percentages from? \$\endgroup\$
    – Jason S
    Apr 16, 2018 at 21:16

[First off, the "RS" in RS-232 denotes "Recommended Standard", which it was when it was released in the 1960s. Since eons however it is an accepted standard by the EIA as EIA-232, and the old name was officially abandoned since. But it seems there's nothing like killing old habits :-) ]

On topic: the allowed clock tolerance depends on the detection method. IIRC the old 68HC11 sampled a few times at a bit start, a few times in the middle of a bit, and the at the end. (Sampling occurred at 16x bit rate.) This allows for half a bit difference on the last bit. Most communication on EIA-232 :-) consists of 10 bits (1 start, 8 data, 1 stop), so half a bit in the stop bit is 5%.

  • 4
    \$\begingroup\$ A UART packet is [START][DATA][PARITY][STOP], so 0x00 would be [0b1][0x00][0b0][0b00] (parity optional, stop variable length). That exception makes sense for some I2C/TWI situations, though. \$\endgroup\$
    – tyblu
    Dec 7, 2010 at 13:05
  • \$\begingroup\$ Indeed, stop-start is always an edge \$\endgroup\$
    – user17857
    Jan 13, 2013 at 13:44
  • \$\begingroup\$ You have to take into account both the tolerance of the receiver and the tolerance of the transmitter. So, effectively, you have to halve the 5% tolerance. This results in a maximum tolerance of 2.5% on the transmitter and a maximum tolerance of 2.5% on the receiver. \$\endgroup\$
    – NZD
    Feb 2, 2020 at 21:58

Bear in mind error is peak-to-peak - this can be an issue at high baudrates on a jittery clock - RC oscillators can have quite a lot of jitter, so a 1% (avarage or RMS) calibrated clock may actually have instantaneous errors larger than that. At lower baudrates this will tend to get avaraged out.


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