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I've been doing research to find how much faster register access is compared to primary memory. I find the ration is about 100 times faster, can that be correct, has it always been about that number of is this number increasing or decreasing?

I read that the microprocessor can access the register file twice every clock cycle and that a primary memory access can take 50 ns. A modern computer microprocessor's clock cycle is abt 4 GHz, which is about 10^6 cycles per second i.e. about 1 cycle per nanosecond (?)

Are my number appromimately correct or am I wrong by factor 10 somewhere?

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I think it's a little less than that, but the ratio has been getting higher over time, at least from the 70s onwards.

1 cycle per nanosecond = 1GHz. 4GHz is right on the high end and is four times as fast. However a latency of 50ns is a bit high as an estimate, this article on latency is quoting numbers around 10ns in 2009. If I use that number I get a ratio of 80 times as fast; I suspect real world numbers will be 50-100 depending on configuration.

This is why having lots of cache on-die with the processor makes such a big difference.

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    \$\begingroup\$ The Column Access Strobe Latency from the article you linked is not the total latency of a memory access. Aside from assuming a row hit, this does not account for the transfer time (typically four DRAM cycles)--not supporting critical word first can simplify the design--and ignores overhead in cache tag checking, the on-chip network, the memory controller, etc. 50ns is probably about right. \$\endgroup\$ – Paul A. Clayton Jul 17 '13 at 12:52

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