6
\$\begingroup\$

I understand that PCI express is a serial connection with clock embedded with the signals. So, what is the utility of the reference clock signal? What is it used for?

Does the reference clock have to be matched and routed with the data lanes? Is there a possibility of reference clock being skewed?

\$\endgroup\$
1
  • 1
    \$\begingroup\$ A separate clock always leads to clock skew problems at high speed. PCI express has it's clock embedded in the data lanes (is it not?). So what purpose does the extra clock line serve? each lane is a self contained full duplex communication system. \$\endgroup\$
    – Lord Loh.
    Jul 17, 2013 at 10:15

3 Answers 3

8
\$\begingroup\$

The shared reference clock is required so that all of the transmitters are frequency locked and no frequency offset compensation is required in the receivers. Obviously they will have to recover the clock and compensate for the phase, but the phase will be fixed (well, more or less). Without it, idle codewords would need to be inserted or removed periodically to compensate for drift in reference clock frequency between the transmitter and receiver. Protocols like 10G Ethernet have interframe gaps between packets that can be extended or contracted to compensate for up to 200 ppm of frequency offset between link partners. PCIe does not support this, and so requires a shared reference clock.

\$\endgroup\$
8
  • 2
    \$\begingroup\$ PCIe definitely does support separate link partner reference clocks; this is the reason the SKP ordered set exists. A shared reference clock is often used, but is not required. \$\endgroup\$ Sep 21, 2016 at 8:24
  • 1
    \$\begingroup\$ Interesting. Do you know the reasoning for using a shared reference clock, then? Cost saving? Spread spectrum support? \$\endgroup\$ Sep 21, 2016 at 12:02
  • 1
    \$\begingroup\$ Basically for cost reasons, particularly in consumer kit; plug-ins can use either a shared reference or their own independent clock. Motherboard designs often use a shared (buffered) reference. Any link type that supports independent references will normally support a shared reference but going across cables and PCB interconnects in multi-PCB boxes make this difficult. \$\endgroup\$ Sep 21, 2016 at 12:09
  • 1
    \$\begingroup\$ Spread spectrum for independent clocks is a bit difficult, but version 2 and 3 requires a receiver to tolerate the full 20nsec (0.5% spread) timing interval error introduced by spread spectrum. See the 'Data-clocked RX architecture' in the specification. The clock phase noise definitions changed pretty drastically between versions 1 and 2 / 3. The frequency of SKP transmissions needs to be carefully evaluated, though. \$\endgroup\$ Sep 21, 2016 at 12:51
  • 2
    \$\begingroup\$ The spread spectrum is indeed applied to the data. The receiver needs to be SRIS (Separate Reference clocks with Independent Spread spectrum) compliant for proper link operation. \$\endgroup\$ Sep 21, 2016 at 13:37
12
\$\begingroup\$

The reference clock is multiplied up through a PLL to the line rate (2/5Gb/sec, 5Gb/sec, 8Gb/sec for versions 1.x, 2.x and 3.x respectively); this determines the data rate from a transmitter.

The clock is effectively embedded in the data stream by using line coding which for the 2.5Gb/sec and 5Gb/sec is 8 bit / 10 bit and 128bit/130bit (see third paragraph) for gen.3 (8Gb/sec). Note that this coding is derived from the reference clock (as multiplied up).

This allows the receiver to use standard clock recovery techniques.

It is not necessary to have a common reference clock (for all versions); this is the reason the SKP (skip) ordered set exists. This allows a difference between reference clocks at each different link partner (the specification permits the reference clock to be +/- 300ppm so a relatively inexpensive device may be used) and receivers implement elastic buffers to cross the timing domains.

This clock domain crossing mechanism eliminates skew issues between clocks.

Note that a common reference clock which is almost guaranteed to have a phase difference at link partners will still need a 1 bit FIFO (as was used in Hypertransport which did require a common reference clock).

In one design, I had 8 potential PCIe link partners; here is where a shared reference clock makes sense.

I used one master reference clock ($20) and a single 8 channel clock buffer ($20), a lot cheaper than 8 reference clocks.

For designs where the links traverse cables and/or multiple connectors in multi-PCB designs, shared references are not really suitable as the reference clock at each link partner needs to be nice and clean.

\$\endgroup\$
8
\$\begingroup\$

The clock is not embedded with the data signal, it can be recovered from the data. The recovery can be done in a number of ways, mostly based around phase-locked-loops, but the design is simpler if you have a reference clock to work from. The skew for a particular card is fixed once it's plugged in, so all that's required is an adjustable phase offset between the reference clock and the data lines.

Using the same refclk avoids problems if one of the endpoints has poor temperature compensation and drifts away from the correct speed.

The clock can be multiplied up by a PLL and used for other purposes on the card, saving you a crystal on the card.

http://comments.gmane.org/gmane.technology.electronics.signal-integrity/19400

\$\endgroup\$
3
  • 1
    \$\begingroup\$ How is embedding the clock source different from recovering a clock? Is it something to do with channel encoding? Something like RZ, NRZ or Manchester? Does the reference clock have to be matched with the data lanes? \$\endgroup\$
    – Lord Loh.
    Jul 17, 2013 at 11:48
  • \$\begingroup\$ I don´t fully understand this explanation. Can the clock be recovered from the data stream wihtout the REFCLK or not? Because If it can, then I don´t see an effect of drift...? \$\endgroup\$
    – Junius
    Jul 1, 2016 at 8:36
  • 1
    \$\begingroup\$ For the record, you don't need refclk on the receiver if your device is compliant with rev2 or higher of the PCIe spec. The architecture is referred to as 'data clocked refclk'. \$\endgroup\$ Aug 10, 2016 at 0:32

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.