NAND gates are only the most economical if your method of implementation provides NAND gates as a primitive element, such as a CMOS ASIC. Most FPGAs use multiplexers to implement logic functions so there is no benefit to reworking your logic equation to put it in terms of NAND operations.
It's also true that CMOS NAND gates tend to be smaller (for a given drive requirement) than NOR gates. NAND gates have NMOS transistors in series and PMOS transistors in parallel, and since the carrier mobility in NMOS is 2-3x better than in PMOS the NAND gate can be implemented with NMOS and PMOS transistors of comparable physical dimensions. In other words, if the NMOS and PMOS transistors are about the same size, a NAND gate will have about the same rise and fall time on the output but a NOR gate (with PMOS in series) will have a rise time that is much slower than the fall time.