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I have the following Boolean equation:
A + (B + A)'
From many suggestions I know that it is economical to use NAND gates to implement this equation. I can design a logic circuit of this equation using NAND gates but I don't know why NAND gates are economical for this equation?
NAND gates are only the most economical if your method of implementation provides NAND gates as a primitive element, such as a CMOS ASIC. Most FPGAs use multiplexers to implement logic functions so there is no benefit to reworking your logic equation to put it in terms of NAND operations.
It's also true that CMOS NAND gates tend to be smaller (for a given drive requirement) than NOR gates. NAND gates have NMOS transistors in series and PMOS transistors in parallel, and since the carrier mobility in NMOS is 2-3x better than in PMOS the NAND gate can be implemented with NMOS and PMOS transistors of comparable physical dimensions. In other words, if the NMOS and PMOS transistors are about the same size, a NAND gate will have about the same rise and fall time on the output but a NOR gate (with PMOS in series) will have a rise time that is much slower than the fall time.
Using something else like AND and NAND gates would work and make sense but the reason NAND gates are 'economical' is because all boolean equations can be implemented using combinations of NAND gates.
It's called functional completeness.
NAND gates require less components (e.g. transistors) to create than other gates and for this reason they can be smaller and more financially economical. Also, all logic can be represented with NAND gates.
