# Parallel MOSFETs and Gate Drive Capability

I'm trying to design a Full-Bridge which can handle upto 330 A (@ 12V). I'm paralleling 3 MOSFETs per leg, and I think I've found a low enough RDS(on) MOSFET to make this somewhat practical. Here's a schematic of the parallel MOSFETs in Half-Bridge configuration:

All transistors are AUIRF1324S-7P and each resistor in the above schematic can be assumed to be about 5Ω. The power dissipation in each MOSFET for 111A is 20W. I am managing this heat by a surface mount sink and a fan. I've written how I arrive at the 20W figure below, in case it matters.

My main concern now is switching losses. The max. total gate charge of the MOSFET is 252nC - so for each leg the total gate charge becomes 756 nC (3*252 nC). If I use a run-of-the-mill driver with 2 A output capability, the switch on time is t = Q/I = 750 nC/2 A = 375 nS! My guess is that I will have a lot of switching losses if I drive my MOSFETs this slow. This is where I'm confused: what do I need to do switch these MOSFETs faster? Use a higher current rated driver?

Assuming I use a 5A rated driver, the time becomes 150 nS. At a frequency of 30KHz, will a switch on time of 150 nS present significant switching losses? If so, suppose I go with even higher rated current driver, how do I ensure that my source (a 12V Lead-Acid batt.) is able to handle current spikes upto 10A?

Essentially, my question boils down to: if 150 nS presents significant switching losses at 30KHz, what do I need to do in order to drive my FETs even faster?

Of course, this all assumes there are no gate resistors! The gate resistor will slow down the switch on even further! But most of the papers on Parallel MOSFETs suggest gate resistors are necessary to prevent ringing.

Conduction Loss Calculation:

The FET's rds(on) @ 175 °C is 1.6 mΩ. With each FET handling 110 A, the power dissipated is ~20W. I want to be able to maintain a temperature of 125 °C on these devices (they are rated for 175 °C) with an ambient temperature of 40 °C. So, (125-40)/(20) = 4.2 °C/W. Considering that the device's thermal resistance between junction to case is 0.5 °C/W, I need a heat sink with lower thermal resistance than 3.7. The heat-sink that I've found provides 3 °C/W at 300 LFM airflow. So I feel I have this area covered (I hope, anyway!).

• Gate resistors would not be required if an independent gate driver is used for each gate - and I'm not sure you could successfully use a single gate driver for multiple MOSFETs anyway. – Anindo Ghosh Jul 17 '13 at 18:30
• If there are separate gate drivers, the design must be careful that they all switch at the same time, otherwise one MOSFET will be forced to pass all the current. Three times the current means nine times the power, so this is not a condition that can be allowed to persist for very long. – Phil Frost Jul 17 '13 at 18:37
• @AnindoGhosh Phil highlights my concern regarding a separate driver for each MOSFET. But even if I design carefully, I don't think I can say with certainty that each MOSFET in the leg would turn on together - wouldn't each driver chip have a slight variation regarding at what time the outputs go high. The datasheet for LT1158 has a section on parallel MOSFETs which suggests this ought to be possible - of course, they could simply be using MOSFETs with relatively low input capacitance. – Saad Jul 17 '13 at 18:44
• Where is power and ground on the schematic? One issue that you might run into is load sharing. Since the on resistance (Ron) won't be the same for all mosfets, one will take higher amp draw and the other. Also, what voltage are you driving the mosfets with? Make sure the mosfets operate in the saturation region or else they'll behave like a great resistor in triode mode. – NothinRandom Jul 18 '13 at 17:22
• @NothinRandom - I think you've got that wrong. You need to operate the mossiest in the triode mode - saturation mode implies the Vds is higher. It always seems wrong to me that with MOSFETS saturation mode is the constant current part of the curve. With BJTs it is the other way round. kevin – Kevin White Jun 23 '15 at 20:45

There are many losses associated with switching, but it sounds like you are most concerned about the additional thermal load introduced into the MOSFETs in the period transitioning between on and off. I thought it would be easy to find some application notes on this, but surprisingly it wasn't. The best I found was AN-6005 Synchronous buck MOSFET loss calculations with Excel model from Fairchild, the relevant parts of which I'll summarize here.

During the switching transition, the voltage and current in the MOSFET will look approximately like this:

The switching losses we are going to calculate are those in periods $t2$ and $t3$ due to the voltage and current in the MOSFET. The way to approach this is to calculate the energy of each transition, then convert this into an average power according to your switching frequency.

If you look at just $t2$, $V$ is nearly constant, and $I$ increases approximately linearly, forming a triangle. Thus, the power also increases linearly, and the total energy is the time integral of power. So the energy is just the area of that triangle:

$$E_{t2} = t_2 \left( \frac{V_{in} I_{out}}{2} \right)$$

$t3$ also forms a triangle. In this case, the voltage is changing instead of the current, but still the power makes a triangle, and the calculation of energy is the same.

Since the calculation is the same for $t2$ and $t3$, then it's not really important how much time is spent in $t2$ vs $t3$; all that really matters is the total time spent switching. The energy losses from one switch are thus:

$$E_{switch} = (t_2 + t_3) \left( \frac{V_{in} I_{out}}{2} \right)$$

And, your switching frequency is how many times per second you incur this energy loss, so multiplying the two together gets you the average power loss due to switching:

$$P_{switch} = f (t_2 + t_3) \left( \frac{V_{in} I_{out}}{2} \right)$$

So, taking your calculation of the switching period being $150ns$, and the maximum current being $330A$, and the voltage $12V$, and the switching frequency $30kHz$, the power losses from switching are:

$$30kHz \cdot 150ns \left( \frac{12V \cdot 330A}{2} \right) = 8.91W$$

That's $8.91W$, ideally, shared between three transistors, so only about $3W$ each, which is pretty insignificant compared to your other losses.

This number can be checked for sanity with a simpler model: if you spent $150ns$ switching, and you do it $30000$ times per second, then you can calculate the fraction of the time you spend switching, and make the most pessimistic assumption of the full power of $12V\cdot330A$ being lost in the transistors:

$$\require{cancel} \frac{150 \cdot 10^{-9} \cancel{s}}{\cancel{switch}} \frac{30 \cdot 10^3 \cancel{switches}}{\cancel{s}} \cdot 12V \cdot 330A = 17.82W$$

Of course, over the switching period, the average current and voltage is only half that of the maximum, so the switching losses are half this, which is what we just calculated.

However, I bet in practice, your switching times will be slower. A "$2A$ gate driver" isn't a constant current source as these calculations assume. The real picture is rather more complicated than this simple model. Additionally, the current will be limited by the resistance, and usually more significantly, the inductance of the transistor packages and the traces leading to them.

Let's just say the inductance of the gate driver, transistor package, and traces to it is $1\mu H$. If your gate drive voltage is $12V$, then $di/dt$ is limited to $12V/1\mu H = (1.2\cdot 10^7)A/s$. This may seem like a lot, but on the time scale of $150ns$, it's not. Keeping the inductance low will take some very careful layout.

So, I would say that these calculations show that your switching losses may be manageable, though you won't know for sure until you've made the layout and tested it. Even if you can't reach the ideal of a $150ns$ switching time, the losses are low enough relative to your other problems that you have some margin to do worse and still function.

Your bigger problem is probably getting the three MOSFETs to switch at the same time. Otherwise, one of them will get a disproportionate share of the total current, and thus heat, leading to premature failure.

• Wouldn't having the FETs in parallel ensure that they are on at the same time (using the same gate driver)? I've seen parallel FETs in quite a few places so I assumed it wasn't this hard to do. – Saad Jul 17 '13 at 19:53
• @Saad well, if everything is equal from the driver to each FET, yes. But your layout won't be exactly symmetrical, and the devices aren't exactly identical, so it takes a little care. You want to make them identical to the extent that you can. Adding some series resistance helps damp oscillations between the gate capacitance and stray inductance, and also adding a resistance which you can control makes the other parameters which you can't control less significant. – Phil Frost Jul 17 '13 at 20:03
• thanks! That makes sense. I'm beginning to wonder if I should just go with one large FET per leg. It would make this additional complexity go away - but the problem then would be managing the heat. But if adding the series resistance ensures, somewhat, that the FETs will turn at the same time, then I suppose it's doing. – Saad Jul 17 '13 at 20:06
• @Saad typically, the ringing is enough of a problem in itself to require the resistors, and the added symmetry is just a nice side effect. It's a problem even without parallel FETs, but the parallel FETs make it worse by increasing the capacitance and introducing more unintended inductors. – Phil Frost Jul 17 '13 at 20:09
• @KyranF I doubt it. An IGBT has the output characteristics of a BJT, including a collector-emitter saturation voltage that's a little something over 0.2V regardless of current. For high voltages, this beats a MOSFET, but when all we need to block is 12V, it's quite feasible to manufacture a MOSFET with an $R_\text{DS(on)}$ sufficiently low to get the drain-source voltage below what it would be for an IGBT. A low $R_\text{DS(on)}$ becomes increasingly hard for a higher $V_\text{DS(max)}$, and at some point IGBTs are better. More than 12V, though. – Phil Frost Oct 18 '14 at 18:49

This is a lot of current to handle. You don't say here what the full bridge is driving, so I'm thinking a transformer followed by a diode bridge and then to the LC filter and load. I'm also going to assume the bridge is just chopping at 50% for each leg.

I think you may be being a little conservative with the conduction losses, because each FET will have at most a 50% duty cycle. For the AUIRF1324 conduction losses with 110 amps per FET you would expect:

$P_{\text{cond}}$ = $\text {DC } i_ {\text {rms}}^2 R_ {\text {ds}}$ = $\text{(0.5)} \text{(110)}^2 \text{(1.4)}\text{(0.0008)}$ = 6.8W

Where I've used a nominal value for $R_ {\text {ds}}$ (0.8 mOhms) and a multiplier of 1.4 for $T_j$ of 125C and the duty cycle (DC) of 50%.

You can make an estimate of the switching loss (of each of the top FETs) by using:

$P_{\text{sw}}$ ~ $\frac{I_o f_{\text{sw}} V_{\text{in}} Q_{\text{sw}}}{I_g}$ Where $I_g$ = $\frac{V_{\text{gmax}}-V_{\text{pl}}}{R_g+R_{\text{driver}}}$ and $V_{\text{pl}}$ is the miller plateau voltage.

So, $P_{\text{sw}}$ ~ $\frac{\text{(110A)} \text{(12V)} \text{(30kHz)} \text{(135nC)}}{\text{0.94A}}$ = 5.7W

Gate switching loss for each FET would be:

$P_{\text{gate}}$ = $f_{\text{sw}} Q_g V_{\text{gmax}}$ = $\text{(12V)} \text{(30kHz)} \text{(175nC)}$ = 0.063W

Optimal FET loss will be when $P_{\text{cond}}$ = $P_{\text{sw}}$ + $P_{\text{gate}}$ . So, this FET is pretty close to optimal.

Easiest way to drive the FETs will be to use an H-bridge driver like an LM5104. Whichever gate drive you use, it will need to be located as close as possible to the FETs to minimize gate circuit inductance ($L_g$). Gate circuit resistance $R_g$ + $R_{\text{driver}}$ will need to be no less than $\sqrt{\frac{L_g}{C_{\text{iss}}}}$ to prevent gate ringing.

When you parallel the FETs make sure each has its own gate resistor.

One more thing to think about

Be aware that switching power supplies show a negative input impedance. This means that if the input impedance of the full bridge is less than the output impedance of the input power source, the system will oscillate. 330A from 12V is 36 mOhms. So, the input power source, including any input filter you may have, will need an output impedance of about 18 mOhms to avoid oscillation.

What do I need to do in order to drive my FETs even faster?

I've read the answers but I don't think anyone's said drive the gate voltage a few volts below the source voltage - this means you can discharge the gate fully in a quicker time and during the period those FETs are off you can return the gate voltage (at relative leisure) back to the source voltage (or maybe even a tad higher) ready for the next onslaught.

The high-side FETs - these are source followers and I'm presuming it's because you can't find a P channel that does the job. A little bit more care needs to be taken driving these because the source is following the output. I'd be tempted to use a transformer to provide an isolated supply for those FET drivers and use a really fast transformer for transferring the drive signal up to that circuit. Again, taking the gate negative when turning off is needed I believe.

Here's a rough sketch of how you'd drive the source followers with just a drive transformer, although I think you'll need a power transformer and driver as well as just the drive transformer: -

How do I ensure that my source (a 12V Lead-Acid batt.) is able to handle current spikes upto 10A?

How will this source handle the 330A is my question? Current spikes are solved with really high grade capacitors close to the FETs and good layout practises.

• Could you elaborate on the transformer idea? I haven't heard of transformers driving a FET. FWIW, the parallel MOSFETs are for the full-bridge that I asked about a few days ago, which you answered. – Saad Jul 17 '13 at 20:51
• For the top FETs, the drive to the gate, in order to keep the FET on has to be x volts above the source - as the source is also the load voltage, it makes the gate voltage drive non-trivial from the viewpoint of ground/0V. This means you need to raise the gate drive (relative to ground) to the same potential as the source and of course this is a little tricky so I'd "float" some power up to the top fet's source via a transformer so that the driver circuits were driving a gate voltage relative to the source (output voltage) BUT I need also to couple the gate signal up there too. Makes sense? – Andy aka Jul 17 '13 at 21:33
• Hi @Saad yes, I remember!! This is going to be a tricky one but gut-feeling tells me it's going to work. Can you not find P channel FETs for the top transistors? – Andy aka Jul 17 '13 at 21:35
• no, digikey doesn't return with P-Channel MOSFETs for my parameters. I'll look again. Question: Why not just use a gate driver IC? Why 'bother' with a transformer? – Saad Jul 17 '13 at 21:46
• Andy, would it be possible for you to give me a rough schematic for this? Googling "Transformer Driving FET" doesn't return much. – Saad Jul 17 '13 at 22:24

What's letting you down here is the speed of the rise time(Tr) of the AUIRF1324S-7P which is a massive 240ns.

I can think of a MOSFET that's in a package that can handle 240A, is silicon limited to 1000A, so any 5ns switching time where one FET is on before another will not damage the junction. It retails for less than \$5 each on outperforms the AUIRF 5 fold in all speed measurements. You would only need two together to produce 500A.

You should check the actual gate current source graphs for the drivers because some that are averaged rated at 2.5A in the brochures have maximum ratings of 3.8A at Vgs max

Many of the drivers rated for 2A were only managing a max of 1.96A at Vgs max