39
\$\begingroup\$

We had a very short FPGA/Verilog course at university (5 years ago), and we always used clocks everywhere.

I am now starting out with FPGAs again as a hobby, and I can't help but wonder about those clocks. Are they absolutely required, or can an FPGA-based design be completely asynchronous? Can one build a complex bunch of logic and have stuff ripple through it as fast as it can?

I realise that there are a whole lot of gotchas with this, like knowing when the signal has propagated through all parts of the circuit and the output has stabilised. That's beside the point. It's not that I want to actually build a design that's entirely asynchronous, but just to improve my understanding of the capabilities.

To my beginner eye, it appears that the only construct that absolutely requires a clock is a reg, and my understanding is that a typical FPGA (say, a Cyclone II) will have its flip-flops pre-wired to specific clock signals. Is this correct? Are there any other implicit clocks like this and can they typically be manually driven by the design?

\$\endgroup\$
  • 3
    \$\begingroup\$ I know Simon Moore at the university of Cambridge did a lot of research into asynchronous design, including getting a test chip fabricated. It requires an entirely new set of design tools, and has strange side effects: execution speed inversely proportional to temperature, for example. \$\endgroup\$ – pjc50 Dec 8 '10 at 15:32
27
\$\begingroup\$

A short answer would be: yes; a longer answer would be: it is not worth your time.

An FPGA itself can run a completely asynchronous design no problem. The result you get is the problem since timing through any FPGA is not very predictable. The bigger problem is the fact that your timing and resultant design will almost definitely vary between different place and route sessions. You can put in constraints on individual asynchronous paths making sure that they do not take too long, but I'm not quite sure that you can specify a minimum delay.

In the end it means that your design will be unpredictable and potentially completely variable with even a slight design change. You'd have to look through the entire timing report every time you change anything at all just to make sure that it would still work. On the other hand, if the design is synchronous, you just look for a pass or fail at the end of place and route (assuming your constraints are setup properly, which doesn't take long at all).

In practice people aim for completely synchronous designs but if you need to simply buffer or invert a signal, you don't need to go through a flip flop as long as you constrain it properly.

Hope this clears it up a bit.

\$\endgroup\$
  • 3
    \$\begingroup\$ I had to use some devices with asynchronous FPGA designs. They were hard to work with. Please at least use timing constraints \$\endgroup\$ – Tim Williscroft Dec 7 '10 at 22:00
  • 1
    \$\begingroup\$ While it's true that it's possible to implement asynchronous designs with an FPGA, most FPGAs are built to support specifically synchronous designs. They have plenty of resources (PLLs, clock distribution circuits, and huge amount of flip-flops) which will be wasted in an asynchronous design. \$\endgroup\$ – Dmitry Grigoryev Dec 9 '15 at 11:42
  • 2
    \$\begingroup\$ This answer doesn't provide particularly good advice. You can create a clockless FPGA and it actually simplifies place and route, removes a ton of problems regarding timing requirements, and due to fine grained pipelining can have measurably higher throughput. The real problem comes when you try to map a clocked circuit to a clockless FPGA because they have very different timing characteristics. It can be done, it just requires a bit more front-end processing to do the conversion. vlsi.cornell.edu/~rajit/ps/rc_overview.pdf \$\endgroup\$ – Ned Bingham Mar 2 '17 at 19:06
20
\$\begingroup\$

"Can one build a complex bunch of logic and have stuff ripple through it as fast as it can?" Yes. Entire CPUs have been built that are completely asynchronous -- at least one of them was the fastest CPU in the world. http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU

It irks me that people reject asynchronous design techniques, even though they theoretically have several advantages over synchronous design techniques, merely because (as others here have said) asynchronous designs are not as well supported by the available tools.

To me, that's like recommending that all bridges be made out of wood, because more people have woodworking tools than steel-working tools.

Fortunately, some of the advantages of asynchronous design can be gained while still using mostly synchronous design techniques by using a global asynchronous local synchronous (GALS) design.

\$\endgroup\$
  • \$\begingroup\$ I feel exactly the same way about the modern tendency to route PCBs on a square grid, although the benefits of migration are much less significant. \$\endgroup\$ – Roman Starkov Jan 16 '11 at 0:30
  • \$\begingroup\$ @romkyns - That's more down to the fact that writing PCB software that uses non-rectilinear grids is hard. \$\endgroup\$ – Connor Wolf Feb 28 '11 at 23:39
  • 1
    \$\begingroup\$ @supercat: I suspect you're alluding to four-phase logic. It's one of the multi-phase clock signals that seems to be forgotten. \$\endgroup\$ – davidcary Sep 11 '11 at 3:33
  • 1
    \$\begingroup\$ @davidcary: Sort of, except both "phases" on one wire--one phase being controlled by the rising edge, and one by the falling edge. Basically, I'd divide latch clocks into four categories: clean rising, clean falling, late rising, late falling. Latches clocked by (L/CB) a clean rising or falling edge could take data from any rising or falling edge. L/CB a late rising edge could take data from L/CB clean rising edge any falling edge. L/CB by late falling edge could take data from L/CB clean falling or any rising. \$\endgroup\$ – supercat Oct 12 '11 at 15:00
  • 1
    \$\begingroup\$ @davidcary: Provided that the fastest propagation time for any latch exceeds the longest hold time, and provided that the longest signal path from a clock edge, through clock gating logic and "late" latches triggered by that edge, to any latch triggered by the following edge, does not exceed the minimum time between clock edges, I would think such a design should be completely reliable and free of internally-generated metastability under any combination of propagation delays. \$\endgroup\$ – supercat Oct 12 '11 at 15:05
5
\$\begingroup\$

One factor not yet mentioned is metastability. If a latching circuit is hit with a sequence of input/transitions such that the resulting state would depend upon propagation delays or other unpredictable factors, there is no guarantee that the resulting state will be a clean "high" or "low". Consider, for example, an edge-triggered flip flop which is currently outputting a "low", and has its input change from low to high at almost the same time as a clock edge arrives. If the clock edge happens long enough before the input change, the output will simply sit low until the next clock edge. If the clock edge happens long enough after the input change, the output will quickly switch once from low to high and stay there until the next clock edge. If neither of those conditions applies, the output can do anything. It might stay low, or quickly switch once and stay high, but it might stay low for awhile and then switch, or switch and then some time later switch back, or switch back and forth a few times, etc.

If a design is fully synchronous, and all the inputs are double-synchronized, it is very unlikely that a timing pulse would hit the first latch of a synchronizer in such a way as to cause it to switch at the perfect time to confuse the second latch. In general, it is safe to regard such things as "just won't happen". In an asynchronous design, however, it is often much harder to reason about such things. If a timing constraint on a latching circuit (not just flip flops, but any combination of logic that would act as a latch) is violated, there's no telling what the output will do until the next time there's a valid input condition that forces the latch to a known state. It is entirely possible that delayed outputs will cause the timing constraints of downstream inputs to be violated, leading to unexpected situations, especially if one output is used to compute two or more inputs (some may be computed as though the latch was high, others as though it were low).

The safest way to model an asynchronous circuit would be to have almost every output circuit produce an "X" output for a little while whenever it switches between "0" and "1". Unfortunately, this approach often results in nearly all nodes showing "X", even in cases which would in reality have almost certainly resulted in stable behavior. If a system can work when simulated as having all outputs become "X" immediately after an input changes, and remain "X" until the inputs are stable, that's a good sign the circuit will work, but getting asynchronous circuits to work under such constraints is often difficult.

\$\endgroup\$
4
\$\begingroup\$

Of course if your design requirements are slow enough that a lot of internal delays are still orders of magnitude longer than times that you care about, then it's not a problem, and you can look at the timing report to keep an eye on this, but there's a limit to what you can usefully do with no internal state info. If you just want to make something like a 100 input multiplexer then fine, just remember that each input will have a different propagation delay. In fact you may get some interesting and chaotic effects with large numbers of unpredictable-delay oscillating feedback loops - maybe a fully async FPGA based synthesiser could be the next 'analogue'..

\$\endgroup\$
4
\$\begingroup\$

Yes, you can. You can ignore the flipflops completely and build it all out of LUTs. And/or you can use the state elements of most Xilinx FPGAs as (level triggered) latches instead of (edge-triggered) flipflops.

\$\endgroup\$
  • 3
    \$\begingroup\$ A danger with that is that unless one restricts the logic compiler, it may produce logic which has negative propagation time for some gates. For example, if one specifies X=(someComplexFormula) and Y=X & D, and if the compiler substitutes that formula for X and determines that X & D is equivalent to A & D, the compiler might replace compute Y in terms of A and D, rather than in terms of X, thus allowing the computation of Y to proceed faster than that of X. Such substitutions are valid with combinatorial logic, but wreak havoc on asynchronous sequential logic. \$\endgroup\$ – supercat Mar 2 '15 at 15:06
  • \$\begingroup\$ @supercat - I've never worked with Xilinx's tools, but when I've worked with Altera FPGAs, you've always had the option of specifying any critical paths as connected gate modules rather than in RTL, at which point any such optimisations are disabled. \$\endgroup\$ – Jules Jul 15 '18 at 13:31
  • \$\begingroup\$ @Jules: All of my programmable-logic designs have used Abel, which is a somewhat goofy language, but makes it possible to specify things in ways that some CPLDs can implement, but which might pose difficulties for a VHDL or Verilog synthesis tool. For example, on one of my projects, I exploited the fact that Xilinx parts have clock, async set, and async reset, to implement an async-loadable shift register. If I need to do such things in an FPGA, having never used Verilog or VHDL, how should I learn what's needed to do that? BTW, if memory serves, I used T flops for the shifter, and... \$\endgroup\$ – supercat Jul 16 '18 at 17:29
  • \$\begingroup\$ ...the timing was such that the async write could only occur at times when the T input would be low, assuming that if a nop-clock occurred near the start of a write pulse, the async write would extend far enough beyond it as to ensure a stable value, and if the nop-clock occurred near the end, it would simply be latching a still-stable value. I'm not sure how one could efficiently handle such cases in VHDL or Verilog. \$\endgroup\$ – supercat Jul 16 '18 at 17:33
  • \$\begingroup\$ @supercat - taking a similar problem, looking at the Cyclone IV Device Handbook I see that the best approach to the same problem would be to use the "LAB-wide synchronous load" option (a "LAB" is a group of 16 logic elements, so if the size of such a register doesn't end up a multiple of 16 bits then some bits will be wasted, but this seems the most useful option anyway). I now have two options: I can write functional verilog that will require the synthesis tool to pick a way of implementing the register required (which would usually be the best option), or, if I have strict timing ... \$\endgroup\$ – Jules Jul 16 '18 at 23:47
3
\$\begingroup\$

As @Andrey pointed out it is not worth your time. Specifically the tools don't do this, so you would be completely on your own. Plus since they have built-in registers, you wouldn't save anything by not using them.

\$\endgroup\$
3
\$\begingroup\$

Really there are THREE types of designs.

  1. Combinatorial. There are no clocks and no feedback paths and the system has no "memory". When one or more input changes the changes ripple though the logic. After some time the output settles into a new state where it remains until the inputs change again.
  2. Synchronous sequential. A system is built out of registers and blocks of combinatorial logic, the registers are clocked by a small number (often 1) of clocks. If there are multiple clocks then special precuations may be needed on signals that pass from one clock domain to another.
  3. Asynchronous sequential. There are feedback paths, latches, registers or other elements that give the design memory of past events and that are not clocked by easilly analysed clock lines.

In general when synthisizing/optimising combinatorial logic the tools will assume that all that matters is what the final result is and the maximum time needed to settle on that result.

You can build a design that is purely combinatorial and it will get to the right result. The outputs may change in any order and may change several times before reaching their final values. Such designs are very wasteful of logic resources. Most logic elements will spend most of their time sitting idle whereas in a sequential system you could have reused those elements to process multiple data items.

In a sequential synchronous system all that matters is that the outputs of the combinatorial block have settled to their correct state when they are clocked into the next flip flop. It doesn't matter what order they change in or whether they are glitches along the way. Again the tools can easilly turn this into logic that provided the clock is slow enough gives the right answer (and they can tell you if the clock you want to use is slow enough).

In an asynchronous sequential system those assumptions go out of the window. Glitches can matter, order of output changes can matter. Both the tools and the FPGAs themselves were designed for synchronous designs. There has been much discussion (google asynchrous FPGA design if you want to know more) about the possibility of implementing asynchrnous systems either on standard FPGAs or on specilly designed ones but it still lies outside mainstream accepted design practice

\$\endgroup\$
2
\$\begingroup\$

Yes. If you have no process type constructs then it shouldn't do things like inferring registers. There will be things like onboard memory that require clocks, although if you really want to you could probably generate these asynchronously.

\$\endgroup\$
  • 1
    \$\begingroup\$ Did you mean to make this a single answer? \$\endgroup\$ – Kevin Vermeer Dec 7 '10 at 21:33
1
\$\begingroup\$

FWIW I thought I should add that one obvious goal in asynchronous logic solutions woukd be the global reduction in power consumption.

Those global clock/PLL/buffers burn lots of Joules.

As FPGA solutions meander into battery powered arenas (e.g, Lattice Icestick) then this aspect will acquire much more attention.

\$\endgroup\$
  • \$\begingroup\$ This is a good point, although it's worth considering that a badly designed combinatorial circuit performing the same operation as a sequential circuit could in some cases make a lot of transient transitions as partial results are calculated and the final output is updated to account for them, and in CMOS circuits (as most FPGAs are) power consumption is roughly proportional to the number of transitions. Clocks can cause unnecessary transitions, but you can also make a lot of power reductions by disabling clocks in parts of the circuit that aren't needed at the moment. \$\endgroup\$ – Jules Jul 15 '18 at 13:24

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.