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I am running iverilog simulator with a Verilog example of a uart design with testbench. When I run this command,

iverilog -o a.vvp uart_tb.v uart.v  

I get following error:

/uart.v:148: Module uart2 was already declared here: uart.v:1

uart.v code:

 module uart2 (
    reset          ,
    txclk          ,
    ld_tx_data     ,
    tx_data        ,
    tx_enable      ,
    tx_out         ,
    tx_empty       ,
    rxclk          ,
    uld_rx_data    ,
    rx_data        ,
    rx_enable      ,
    rx_in          ,
    rx_empty
    );
    // Port declarations
    input        reset          ;
    input        txclk          ;
    input        ld_tx_data     ;
    input  [7:0] tx_data        ;
    input        tx_enable      ;
    output       tx_out         ;
    output       tx_empty       ;
    input        rxclk          ;
    input        uld_rx_data    ;
    output [7:0] rx_data        ;
    input        rx_enable      ;
    input        rx_in          ;
    output       rx_empty       ;

    // Internal Variables 
    reg [7:0]    tx_reg         ;
    reg          tx_empty       ;
    reg          tx_over_run    ;
    reg [3:0]    tx_cnt         ;
    reg          tx_out         ;
    reg [7:0]    rx_reg         ;
    reg [7:0]    rx_data        ;
    reg [3:0]    rx_sample_cnt  ;
    reg [3:0]    rx_cnt         ;  
    reg          rx_frame_err   ;
    reg          rx_over_run    ;
    reg          rx_empty       ;
    reg          rx_d1          ;
    reg          rx_d2          ;
    reg          rx_busy        ;

    // UART RX Logic
    always @ (posedge rxclk or posedge reset)
    if (reset) begin
      rx_reg        <= 0; 
      rx_data       <= 0;
      rx_sample_cnt <= 0;
      rx_cnt        <= 0;
      rx_frame_err  <= 0;
      rx_over_run   <= 0;
      rx_empty      <= 1;
      rx_d1         <= 1;
      rx_d2         <= 1;
      rx_busy       <= 0;
    end else begin
      // Synchronize the asynch signal
      rx_d1 <= rx_in;
      rx_d2 <= rx_d1;
      // Uload the rx data
      if (uld_rx_data) begin
        rx_data  <= rx_reg;
        rx_empty <= 1;
      end
      // Receive data only when rx is enabled
      if (rx_enable) begin
        // Check if just received start of frame
        if (!rx_busy && !rx_d2) begin
          rx_busy       <= 1;
          rx_sample_cnt <= 1;
          rx_cnt        <= 0;
        end
        // Start of frame detected, Proceed with rest of data
        if (rx_busy) begin
           rx_sample_cnt <= rx_sample_cnt + 1;
           // Logic to sample at middle of data
           if (rx_sample_cnt == 7) begin
              if ((rx_d2 == 1) && (rx_cnt == 0)) begin
                rx_busy <= 0;
              end else begin
                rx_cnt <= rx_cnt + 1; 
                // Start storing the rx data
                if (rx_cnt > 0 && rx_cnt < 9) begin
                  rx_reg[rx_cnt - 1] <= rx_d2;
                end
                if (rx_cnt == 9) begin
                   rx_busy <= 0;
                   // Check if End of frame received correctly
                   if (rx_d2 == 0) begin
                     rx_frame_err <= 1;
                   end else begin
                     rx_empty     <= 0;
                     rx_frame_err <= 0;
                     // Check if last rx data was not unloaded,
                     rx_over_run  <= (rx_empty) ? 0 : 1;
                   end
                end
              end
           end 
        end 
      end
      if (!rx_enable) begin
        rx_busy <= 0;
      end
    end

    // UART TX Logic
    always @ (posedge txclk or posedge reset)
    if (reset) begin
      tx_reg        <= 0;
      tx_empty      <= 1;
      tx_over_run   <= 0;
      tx_out        <= 1;
      tx_cnt        <= 0;
    end else begin
       if (ld_tx_data) begin
          if (!tx_empty) begin
            tx_over_run <= 0;
          end else begin
            tx_reg   <= tx_data;
            tx_empty <= 0;
          end
       end
       if (tx_enable && !tx_empty) begin
         tx_cnt <= tx_cnt + 1;
         if (tx_cnt == 0) begin
           tx_out <= 0;
         end
         if (tx_cnt > 0 && tx_cnt < 9) begin
            tx_out <= tx_reg[tx_cnt -1];
         end
         if (tx_cnt == 9) begin
           tx_out <= 1;
           tx_cnt <= 0;
           tx_empty <= 1;
         end
       end
       if (!tx_enable) begin
         tx_cnt <= 0;
       end
    end

    endmodule

uart.tb code:

`include "uart.v"
module top();

wire       reset          ;
wire       ld_tx_data     ;
wire [7:0] tx_data        ;
wire       tx_enable      ;
wire       tx_out         ;
wire       tx_empty       ;
wire       uld_rx_data    ;
wire [7:0] rx_data        ;
wire       rx_enable      ;
wire       rx_in          ;
wire       rx_empty       ;
wire       loopback       ; 
wire       rx_tb_in       ;
reg        txclk          ;
reg        rxclk          ;

uart_ports ports (
  .reset         (reset       ),
  .txclk         (txclk       ),
  .ld_tx_data    (ld_tx_data  ),
  .tx_data       (tx_data     ),
  .tx_enable     (tx_enable   ),
  .tx_out        (tx_out      ),
  .tx_empty      (tx_empty    ),
  .rxclk         (rxclk       ),
  .uld_rx_data   (uld_rx_data ),
  .rx_data       (rx_data     ),
  .rx_enable     (rx_enable   ),
  .rx_in         (rx_in       ),
  .rx_empty      (rx_empty    ),
  .loopback      (loopback    ) 
);

uart_top tbtop(ports);

initial begin
  $dumpfile("uart.vcd");
  $dumpvars();
  txclk       = 0;
  rxclk       = 0;
end
// Loopback control logic
assign rx_in = (loopback) ? tx_out : rx_tb_in;
// RX and TX Clock generation
always #1 rxclk = ~rxclk;
always #16 txclk = ~txclk;

// DUT Connected here
uart U (
.reset          (reset),
.txclk          (txclk),
.ld_tx_data     (ld_tx_data),
.tx_data        (tx_data),
.tx_enable      (tx_enable),
.tx_out         (tx_out),
.tx_empty       (tx_empty),
.rxclk          (rxclk),
.uld_rx_data    (uld_rx_data),
.rx_data        (rx_data),
.rx_enable      (rx_enable),
.rx_in          (rx_in),
.rx_empty       (rx_empty)
);

endmodule

I didn't find any bug in this code. I am still a beginner in Verilog and cannot debug further. The source code was taken from asic-world.

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  • \$\begingroup\$ Have you tried changing the name of the module? maybe something already exists with that name in your library. Maybe [your initials]_uart \$\endgroup\$ – Iancovici Jul 18 '13 at 11:46
  • \$\begingroup\$ @echad: Yes i had tried changing module name to xyz_uart2 but then error changes to "/uart.v:148: Module xyz_uart2 was already declared here: uart.v:1" \$\endgroup\$ – shailendra Jul 18 '13 at 11:54
  • \$\begingroup\$ Your always block should nest its contents with a begin-end pair. \$\endgroup\$ – travisbartley Jul 18 '13 at 13:21
5
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The testbench for the design has the following line

`include "uart.v"

This line tells the program to read this file as it is necessary for the testbench. However in your command you also specify that this file is to be read.

iverilog -o a.vvp uart_tb.v uart.v  

The file uart.v is read twice, meaning all modules contained are read twice. The error occurs because you read the module twice. Either remove uart.v from the command, or remove the include statement in the testbench.

| improve this answer | |
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  • \$\begingroup\$ I had tried the option suggested but the problem prevails with further errors.I had tried both the options i.e. either removing include uart.v from uart_tb.v or removing uart.v from command line but in both cases, this error comes uart_tb.v:20: error: Unknown module type: uart_ports uart_tb.v:37: error: Unknown module type: uart_top 3 error(s) during elaboration. *** These modules were missing: uart_ports referenced 1 times. uart_top referenced 1 times.` \$\endgroup\$ – shailendra Jul 19 '13 at 6:10
  • \$\begingroup\$ This is a different, unrelated error. You either have module name mismatches, or you are missing some files. \$\endgroup\$ – travisbartley Jul 19 '13 at 6:15
  • \$\begingroup\$ Please download all related files and place them in the same directory. asic-world.com/examples/systemverilog/uart.html \$\endgroup\$ – travisbartley Jul 19 '13 at 6:18
  • \$\begingroup\$ @tra1s: I downloaded other 2 files which were required by uart_tb.v i.e. uart_ports.cv and uart_cb.sv, i dont find that other files are required.Now i am getting a different error in uart_pots.sv ,uart_ports.sv:4: syntax error its interface uart_ports();, i didnt find any syntax error in this file. \$\endgroup\$ – shailendra Jul 19 '13 at 7:10
  • \$\begingroup\$ At uart_ports.sv line 4 there is a SystemVerilog keyword, "interface". The simulation tool you are using will compile only IEEE-1364 (Verilog-95). Note that the sv file suffix stands for SystemVerilog. \$\endgroup\$ – travisbartley Jul 19 '13 at 7:19

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