ARM Cortex M3 (ATSAM3N4B) IACCVIOL Hard Fault

Question

The ATSAM3N4B is an ARM Cortex M3 microcontroller from Atmel. I wanted to ask if anyone can help clarify the IACCVIOL Hard Fault processing.

What I want is the infringing instruction address which the datasheet explains in 10.21.11.1 (pg 182) as:

IACCVIOL

Instruction access violation flag:

0 = no instruction access violation fault

1 = the processor attempted an instruction fetch from a location that does not permit execution.

When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has not written a fault address to the MMAR.

What I want help with is the stacked for the exception return? I don't understand what this refers to.

Is anyone able to help?

Answer 1

Once again, it seems I did not utilize google enough.

Section 10.6.7 of the given datasheet also described on this ARM information center page describes the Exception entry and return process.

So the answer to my question is that faulting instruction address resides on the stack at an offset of +0x18 after entering the exception handler.