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I was running a test case for iverilog provided at this link and had posted a question earlier. When I tested iverilog with uart test case further, found that in uart_tb.v, we are using file uart_port.sv which is s system verilog file and contain a system verilog keyword "interface". Below is the file.

uart_ports.sv:

`ifndef UART_PORTS_SV
`define UART_PORTS_Sv

interface uart_ports(
 output   logic       reset          ,
 input    wire        txclk          ,
 output   logic       ld_tx_data     ,
 output   logic [7:0] tx_data        ,
 output   logic       tx_enable      ,
 output   logic       tx_out         ,
 input    wire        tx_empty       ,
 input    wire        rxclk          ,
 output   logic       uld_rx_data    ,
 input    wire  [7:0] rx_data        ,
 output   logic       rx_enable      ,
 output   logic       rx_in          ,
 input    wire        rx_empty       ,
 output   logic       loopback       , 
 output   logic       rx_tb_in       
);
endinterface

`endif

My question is, does iverilog support system verilog keywords? I can use different version of verilog i.e. verilog 1995, 2001 and 2005 with -g flag, and I tried with -g2005, but still get the error:

uart_ports.v:4: syntax error

Is there any keyword for interface keyword (of System verilog) in verilog or should I consider that either this test case can't be simulated with iverilog or iverilog limitation with System verilog keywords.

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    \$\begingroup\$ Please expend more effort in doing research for your own questions. You should spend at the bare minimum 10 minutes trying to solve your own question. Also, about half of your questions never got marked solved, despite getting good answers for them. Some people ignore questions from such users. \$\endgroup\$ – travisbartley Jul 19 '13 at 8:00
2
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2005 This flag enables the IEEE1364-2005 standard. This is default enabled after v0.9.

2009 This flag enables the IEEE1800-2009 standard, which includes SystemVerilog. The SystemVerilog support is not present in v0.9 and earlier. It is new to git master as of November 2009. Actual SystemVerilog support is ongoing.

If the newest version still gives a syntax error, even when using the 2009 flag, then it does not support that keyword.

Source

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  • \$\begingroup\$ Yups. its still not support interface system verilog keyword.My iverilog version is 0.9.5.iverilog 2009 version is unknown to it but it have a generation flag option as -gsystem-verilog.Got following message when run with -g2009 flag Unknown/Unsupported Language generation 2009 Supported generations are: 1995 -- IEEE1364-1995 2001 -- IEEE1364-2001 2005 -- IEEE1364-2005 \$\endgroup\$ – shailendra Jul 19 '13 at 8:05

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