My task is to design a schematic for a register that has an input of clk and i[7:0] which is an 8 bit binary input interpreted as a number and an output of F which goes high if i was equal was to 127 base 10 two rising edges ago, and which is '0' otherwise. Now I have designed the register having 8 flip flops connected to 8 buses for the input and 8 buses for the output.
How would I go about satisfying the output of F however? Do I need to attach an AND gate to the output? How would I show 127 base 10 two rising edges ago? I am using Xilinx. Thank you!