My task is to design a schematic for a register that has an input of clk and i[7:0] which is an 8 bit binary input interpreted as a number and an output of F which goes high if i was equal was to 127 base 10 two rising edges ago, and which is '0' otherwise. Now I have designed the register having 8 flip flops connected to 8 buses for the input and 8 buses for the output.

How would I go about satisfying the output of F however? Do I need to attach an AND gate to the output? How would I show 127 base 10 two rising edges ago? I am using Xilinx. Thank you!

  • \$\begingroup\$ You have the wrong number of registers. You either need to register everything twice, then make a decision, or make a decision, and register it twice. Or what is probably the most reliable solution: register the inputs once, make a decision using combinatorial logic operating on the outputs of the input registers, and then register the decision, for a total of two register delays. \$\endgroup\$ Commented Jul 20, 2013 at 3:01
  • \$\begingroup\$ How many registers are needed than? This is how I had it looking: i.sstatic.net/FidWG.png \$\endgroup\$ Commented Jul 20, 2013 at 3:06
  • \$\begingroup\$ Depending on the solution chosen, 16, 2 or (8+1)=9. Technically you could also do it in fan-in stages, such as (4+2)=6 or some other sum. You seem to have drawn a bank of four flops comprising a 4-bit register, which is not particularly applicable to your problem. \$\endgroup\$ Commented Jul 20, 2013 at 3:11
  • \$\begingroup\$ So I must start from scratch? Or just add 8 more flip flops? \$\endgroup\$ Commented Jul 20, 2013 at 3:12
  • 2
    \$\begingroup\$ You must start by understanding the problem. Drawing pictures is getting you nowhere. Ignore the registers for a minute and figure out how to decide if the value is 127, then toss an 8 register on the inputs and a single bit one on the decision output. \$\endgroup\$ Commented Jul 20, 2013 at 3:31

1 Answer 1


What you want is an 8-bit comparator that goes high when both inputs match. The output of this can then be delayed by two clk cycles using i.e. D-FFs. Take a look here: http://www.electronics-tutorials.ws/combination/comb_8.html

  • \$\begingroup\$ 8-bit comparator? or 8-input AND gate? \$\endgroup\$
    – tcrosley
    Commented Nov 6, 2014 at 18:09
  • \$\begingroup\$ You need a comparator (consisting of bitwise 'not XOR' and an AND gate for all the bits). You want the output to be HIGH only if both 8-bit inputs are equal. \$\endgroup\$
    – Simon
    Commented Nov 11, 2014 at 9:07

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