# Registers & Buses

My task is to design a schematic for a register that has an input of clk and i[7:0] which is an 8 bit binary input interpreted as a number and an output of F which goes high if i was equal was to 127 base 10 two rising edges ago, and which is '0' otherwise. Now I have designed the register having 8 flip flops connected to 8 buses for the input and 8 buses for the output.

How would I go about satisfying the output of F however? Do I need to attach an AND gate to the output? How would I show 127 base 10 two rising edges ago? I am using Xilinx. Thank you!

• You have the wrong number of registers. You either need to register everything twice, then make a decision, or make a decision, and register it twice. Or what is probably the most reliable solution: register the inputs once, make a decision using combinatorial logic operating on the outputs of the input registers, and then register the decision, for a total of two register delays. Commented Jul 20, 2013 at 3:01
• How many registers are needed than? This is how I had it looking: i.sstatic.net/FidWG.png Commented Jul 20, 2013 at 3:06
• Depending on the solution chosen, 16, 2 or (8+1)=9. Technically you could also do it in fan-in stages, such as (4+2)=6 or some other sum. You seem to have drawn a bank of four flops comprising a 4-bit register, which is not particularly applicable to your problem. Commented Jul 20, 2013 at 3:11
• So I must start from scratch? Or just add 8 more flip flops? Commented Jul 20, 2013 at 3:12
• You must start by understanding the problem. Drawing pictures is getting you nowhere. Ignore the registers for a minute and figure out how to decide if the value is 127, then toss an 8 register on the inputs and a single bit one on the decision output. Commented Jul 20, 2013 at 3:31