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I am trying to recreate this D-Latch using only logic gates:

D-Latch

So far I have this for the latch:

Latch circuit

What am I missing here? There should only be one input of c and an output of A1, so I tried connecting the inverter directly to the output of A1 since there is no input of D allowed. But something is still wrong, because the D input isn't connected directly to the output in that picture but how can I show this using only logic gates and not directly having D as input?? Thank you!

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Take a look at: Wikipdia: D-Latch

Specifically, this figure:

enter image description here

The inverting buffer is already required from the D input, and inverting Q to the input of D is a double negative.

Note that the lower And gate has a non-inverted input form D, so you could just move the not gate from the top and gate to the bottom.

The "un-optimized solution":

schematic

simulate this circuit – Schematic created using CircuitLab

Using the double not-gate optimization:

schematic

simulate this circuit

"Cheating" and getting rid of both not gates:

schematic

simulate this circuit

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  • \$\begingroup\$ If I take out the NOT gate what goes on the input of the AND gate? Do I attach that to A1? \$\endgroup\$ Jul 20, 2013 at 5:18
  • \$\begingroup\$ I updated with actual schematics showing the basic solution and two possible optimized equivalents. \$\endgroup\$ Jul 20, 2013 at 5:35
  • \$\begingroup\$ Thank you! Since I am only suppose to have an output of A1, I can ignore using !A1 as another output and just leave it blank correct? \$\endgroup\$ Jul 20, 2013 at 16:08
  • \$\begingroup\$ Yep, it's perfectly fine to leave it unconnected as an output. \$\endgroup\$ Jul 20, 2013 at 16:58
  • \$\begingroup\$ Thank you so the final circuit you designed should be equivalent to the one in my original post. I appreciate it! \$\endgroup\$ Jul 20, 2013 at 17:50

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