I am new to digital logic design and would like to know why a flip-flop is also known as a latch?
Because the electronic device reminded engineers of both this item:
and this one:
In the first case, the devices have two states: flipped (in contact with heel) and flopped (not in contact with heel). In normal use they alternate continuously between those two states at about 1Hz.
In the latter case, you can change the object's state from open (unlatched) to closed (latched) by pushing the device. Once in the second state it cannot be returned to the first state by more pushing, you have to apply a specific reset operation to go from closed (latched) to open (unlatched).
In general, "flip-flop" and "gated latch" are synonyms. However, the term "flip-flop" is often used when referring to "edge-triggered flip-flop" (just because it is shorter). When people speak about "D flip-flop" the usually refer to "D edge-triggered flip-flop", however when you hear "JK flip-flop" it can refer to both "JK edge-triggered flip-flop" and "JK gated latch".
In different groups of engineers there are different consensuses as to the usage of these terms. However, if you understand the basic concepts you'll be able to determine the type of the element in question by the context.
You can see my answer to other question, where I tried to explain the difference between these terms.
A simple "RS" (reset/set) latch contains two interconnected switchable elements (typically NAND gates); when using NAND gates, one input will be wired to each gate, wired such that driving it low will force its associated gate high; if the other gate was high at the time, that gate will then go low. When an input is used to flip one gate (make it go high), the other gate will flop (go low). Hence, "flip flop".
A transparent "D" latch uses some gates to convert a "data" input and an "enable" input into RS signals which then drive an RS latch. Any time the enable signal is inactive, the R and S outputs will be as well. When enable is active, either R or S will be activated, depending upon the state of the "data" input. Thus, when enable is active, one gate of the RS latch will go high and low to match state of the data input, and the other will go low and high the opposite way; deactivating enable will cause the output gates to retain their current state until enable goes active again.
An edge-triggered register may be implemented by using two D latches in sequence, the first receives the data input and a clock signal; the second receives the data output from the first and the inverse of the clock signal. When the clock input is in the state to enable the first latch, that latch will track the state of the input, but the second D latch will hold whatever it's holding at the moment. When the clock switches state, the first D latch will stop following the state of the input, but the second will start following the state of the first (which should hold whatever the input was holding just before the clock switched state). When the data input changes, it will affect the state of one latch (flip), and then the second (flop).
Once upon a time, "D" transparent latches were more common than edge-triggered registers, and the term "flip flop" was used often to refer to RS latches. Things with edge-triggered clocks were described as having edge-triggered clocks. Today, however, edge-triggered registers are more common than "D" transparent latches, and thus the term "flip flop" is used to describe them. The terms "flip" and "flop" refer to different parts of the internal circuit operation from what they did in an RS latch, and I would prefer using "flip flop" to refer to RS latches (particularly given that many edge-triggered registers don't actually use cascaded transparent latches inside) but the common usage is to describe edge-triggered registers.