I have a simple state machine as part of my Verilog module:
localparam State_IDLE = 3'b000, State_WRITETOLANE1 = 3'b001; reg [2:0] currentState; reg [2:0] nextState; always @(posedge TxByteClk) begin if( rst ) begin currentState <= State_IDLE; end else begin currentState <= nextState; end end always @(*) begin nextState = currentState; case( currentState ) State_IDLE: begin if( TxSync ) begin nextState = State_WRITETOLANE1; end end State_WRITETOLANE1: begin nextState = State_IDLE; end endcase end
TxSync is an input signal. The bizarre behavior I'm seeing is that at the positive edge of the clock when TxSync is high, currentState is set to State_WRITETOLANE1 and as a result nextState is set to State_IDLE. But nextState was never set to State_WRITETOLANE1 in the first place! Why is currentState getting a value that was not even present in nextState? Doesn't the line currentState <= nextState; imply that currentState is the delayed version of nextState?