Each PCI device (when I write PCI, I refer to PCI 3.0, as opposed to PCIe) has two "ranges" - configuration range (CFG) and "memory mapped input-output" range (MMIO). I won't deep dive into the concepts of address spaces and MMIO because it will make the answer too long and complicated. Google them if they are not familiar to you. In short: CFG range is a standard set of registers used to configure the PCI device; MMIO range is a customary set of registers. In other words: CFG ranges are the same across all PCI devices (there might be slight differences, but the majority of registers are standard); MMIO ranges are device specific (NOTE: while the terms "range" and "space" are not synonyms, there is a consensus to call an MMIO range of the device MMIO space. I'll use them interchangeably)
Now, the size of CFG space is standard - there is an upper bound on the number of registers CFG space can contain and it is the same for each PCI device. Usually, the actual number of registers in CFG space is much smaller than the maximal. The size of MMIO space, on the other hand, is not constant. Why? Well, different devices need different number of registers for communication.
Now think about it for a moment: if the size of MMIO space is not constant, then we need to provide the information about this size of a particular device to the computer in some way, right? One option would be to manually define these parameters for each device. It is the way the early computers worked: you really had to configure each device you plug into a computer by hand. Today we are lazy and want the "plug-and-play" functionality - the computer must obtain this info by itself the moment a new device is added.
In order to allow for "plug-and-play" in PCI devices, the concept of MMIO Base Access Registers (MMIO BARs) was introduced. These registers reside in CFG space of each device (I think that there up to five BARs per CFG space are allowed). The flow is as follows:
- a computer knows to search for these registers during a startup
- a computer reads the BARs in order to understand what sizes of MMIO ranges does this device require
- a computer allocates the device's MMIO spaces, which become standard MMIO ranges in the global MMIO space
- a computer writes back to MMIO BARs the addresses assigned for each device's MMIO range in the global MMIO space.
The above 4 stages are known as "enumeration" of the device - i think that it is usually the BIOS who performs devices' enumeration during the startup.
Except for BARs, CFG space of a device contain many more registers. All other writes to CFG space, which is not part of "enumeration" flow, are called "configuration" of the device. This includes runtime configurations such as: interrupt selection, MSI vectors and addresses, device's power states and many more.
In summary: "enumeration" is the flow executed at startup which allocates MMIO ranges to all the devices. "configuration" is all other writes to CFG space of the device (in general, "enumeration" is included in "configuration").
NOTE: this description is simplified. There are more aspects both to "enumeration" and to "configuration".
It seems that you are new to PCIe and want to get a fast introduction. While your desire is totally understandable (it will take you a way more time to understand PCIe if you don't ask questions), I believe that nothing can replace the original spec. The problem is that PCIe spec is written in the manner which assumes that you're familiar with PCI (at least it seemed that way to me) - you need to read it first. So, start by googling
PCI 3.0 specification and
PCIe 2.1 specification. These documents are frustratingly long, but they'll become your bible if you're really going to work with PCIe devices.