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I need to implement the following block.

enter image description here

LD comes from a clocked control input but Adder and Score Register must be built using sequential logic. When control outputs 1, I load my score into Score Register but I don't know how to stop/freeze it because once LD is 1, I will be adding Score Register's output with the BUS, then load and then add it and so on.

How do I make my combinational circuit execute loading only once?

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I think your only option is to use an edge triggered register like the 74173. Otherwise the circuit does not reach a stable state as you described.

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Use a pulse detector circuit to convert the latch signal into a clock signal.

schematic

simulate this circuit – Schematic created using CircuitLab

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