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I'm trying to grasp and understanding of electronics hopefully to work my way up to building an 8 bit computer.

I'm currently digging deeper into Flip Flops, and rather than taking them that they 'just work', could somebody explain to me WHY Q & not Q hold their values based on the following schematic?

enter image description here

I have drawn this schematic out by hand, following it with inputs each time, starting with 1 & 1 for D and CLK, then removing CLK to 0 as it's edge rises, but I always come out with 0 in my hand workings, however I have physically constructed the circuit and it operates as expected.

So can anybody explain HOW and WHY Q holds its value?

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    \$\begingroup\$ Your diagram is incorrect. The right hand NAND Gates should be NOR gates. Also, what you are showing as a clock input is not a clock but an enable. This isn't a D Flip Flop, but more like a transparent latch. \$\endgroup\$ – user3624 Jul 25 '13 at 21:25
  • \$\begingroup\$ @David I think the diagram is correct. I agree that this is a latch, not a FF, but not everyone agrees on those terms. \$\endgroup\$ – Wouter van Ooijen Jul 25 '13 at 21:36
  • \$\begingroup\$ @WoutervanOoijen You're right. There are several ways to do it. One way is (left to right) AND+NOR, and the other is NAND+NAND. I was getting them confused. \$\endgroup\$ – user3624 Jul 25 '13 at 21:44
  • \$\begingroup\$ The general convention is that FFs are edge sensitive while latches are level sensitive. The diagram in the question is a gated D latch and not a DFF. en.wikipedia.org/wiki/Flip-flop_(electronics)#Gated_D_latch The block diagram should not have the ">" clock symbol but an "E" for enable or "C" for control. \$\endgroup\$ – travisbartley Jul 26 '13 at 1:38
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Note that I teach this stuff, so rather than giving you the answer I'll try to let you figure it out for yourself, which is far more usefull in the long term. I hope the other answers won't spoil this approach.

Try to understand the two NANDs at the right side first. When both inputs (S and R) are 1, what will the outputs be? Try for yourself. Assume Q is 1, is that a stable state? And is Q = 0 a stable state?

Now figure out what happens when S = 0 (R still 1).

And what happens when AFTER S = 0 / R= 1 we go back to S= 0 / R = 0.

When you understand that part, take a look at the left two NANDs. What are their outputs when CLC = 0? And what when CLK = 1?

P.S. Two students of mine just completed building a 16-bit CPU from 74HC-level chips (they used ALU chips, which is a bit of cheating IMO). It took them ~ 6 months.

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    \$\begingroup\$ Our freshman low-level computer course had us design a 16 bit mips cpu in a logic simulator and write an assembler for it as a course project, dumping it onto an FPGA afterwards to see it physically work took significantly less time to do than it would take to wire wrap it with 74xxx chips, and (IMO) much more relevant to modern CS/EE, just a suggestion. \$\endgroup\$ – crasic Jul 25 '13 at 22:05
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    \$\begingroup\$ If the suggestion is aimed at me: those students did this on their own, with minimal support from me. Various simulation-level steps were part of the process. The end goal was to have a CPU with physically recognizable ALU, registers, sequencer, etc. \$\endgroup\$ – Wouter van Ooijen Jul 26 '13 at 7:10

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