What topologies are used for ultra-low-power CMOS DACs?

Question

What schematics, topologies or algorithms are suitable for ultra-low-power DAC design? You can assume the following design requirements (they are flexible):

• Full custom CMOS design (this is not a commercial-off-the-shelf shopping question)
• 10% duty rate
• Up to 50 MS/s
• 8-bit input
• Reasonably robust to mismatch, process variation and power supply noise
• Noise and area requirements are flexible
• Should be appropriate for sub-threshold operation due to power supply restrictions
• Power optimization is the highest priority

I am currently considering a timer-based PWM DAC, but I am not certain about the suitability for ULP.

Note that its not possible to provide a full design proposal in the answer, this is a request for relevant techniques. That's why the requirements are just rough estimates to be taken with a grain of salt.

Answer 1

R-2R is never done, it consumes to much area, it matches extremely poorly, has too high parasitics, etc. etc.

Switched capacitor cells and techniques and almost certainly differential design will hold the day.

If your process is digital rich and analog light, then a sigma delta approach will give you the right results.

"Norsworthy, Steven R., Richard Schreier, and Gabor C." Temes. "Delta-Sigma Data Converters : Theory, Design, and Simulation". Ed. Gabor C. Temes,. Wiley-IEEE Press, 1996.

A 8 stage pipeline DAC with 1 bit per stage will also work, but now you will need at least a nice amplifier per stage. Moving to 1.5 bits per stage will yield better results but at the expense of having more logic to interpolate and drive the 1.5 bit stages.

M. Moussavi, R. Mason, and C. Plett, “A Differential Bipolar Stray-Insensitive Quasi-Passive Pipelined Digital-to-Analog Converter with 17.664 MSps Sample Rate and -85 dB THD,” ESSCIRC 2002, pp. 699–702, Sep. 2002.

This is BJT based (shudder) but the concepts behind it are adaptable to CMOS.

For 8 bits a C-2C approach with a pre-charge and then settle will probably work well, but you need P-P or M-M caps. You can't use gate caps for that due to your sub-threshold (and subsequent capacitance change on the gates), but sub-threshold switching probably is OK. Process is unknown. - here is one paper that is OK:

L. cong, “Pseudo C-2C Ladder-Based Data Converter Technique,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, vol. 48, no. 10, pp. 927–929, Sep. 2001.

and ...

L. Terman and L. Heller, “A two-stage weighted capacitor network for D/AA/D conversion,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, Jan. 1979.

I always recommend this paper for those worried about matching:

P. Drennan and C. McAndrew, “A comprehensive MOSFET mismatch model,” INTERNATIONAL ELECTRON DEVICES MEETING, pp. 167–170, 1999.

For subthreshold (translinear circuits) I recommend the authors Wiegerink, Seevinck and Mulder for good texts.

and to finish off, here is a rampDAC paper.

E. Delagnes, D. Breton, F. Lugiez, and R. Rahmanifard, “A Low Power Multi-Channel Single Ramp ADC With Up to 3.2 GHz Virtual Clock,” IEEE Transactions on Nuclear Science, vol. 54, no. 5, pp. 1735–1742, Feb. 2010.