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The xx4517 (http://www.onsemi.com/pub_link/Collateral/MC14517B-D.PDF) is a 16-pin chip which contains two 64-bit shift register units, each of which in turn is divided into four 16-bit registers. Each of the shift units has a pin which may be called "WE" or "PE/OE" which selects between two modes of operation. In one mode, the bit 0 input is latched into the first register, and each of the other registers latches the output of its predecessor. The outputs of all four shift registers are sent to device pins. In the second mode, the drivers for all four outputs are disabled; the first three pins are repurposed so that the second through fourth shift registers will take data from them pins rather than from their predecessor shift registers. The final output pin is simply unused.

It's clear how the device could be useful when the mode pin is strapped low. I can also see how it would be useful to have a means of switching between either of the following pairs of modes:

Intermediate shift values are output and passed to the next stage
Pins are floated but shift-register outputs are passed to the next stage anyway

Pins are floated but shift-register outputs are passed to the next stage anyway
Pins are floated, and shift registers take input from them

I'm curious in what way the mode-function as it actually sits can be practically utilized. In all the cases I can think of where I would sometimes want a device to load the middle taps from external pins, there would be times when I would want it not load middle taps from the external pins but not output anything to them either.

Since parts with the xx4517 pinout have been made for decades while some other kinds of shifter registers have come and gone, and since 14 pins seems to have been at least as common a size for discrete logic as 16 pins, it would seem curious if those pins were never used by any of the circuits where the part has been employed (especially since one can readily imagine other useful purposes to which such pins could have been put). Is there some clever means of using the 4517's WE pin that I'm unaware of? The only thing I can think of would be for applications which only want to use the mid-tap pins as inputs to drive them via 4.7K resistors, and ignore the fact that they'll often be back-driven, but that seems really really icky. Were there better uses?

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  • \$\begingroup\$ Please add a link to the datasheet for this chip. \$\endgroup\$ – jippie Jul 28 '13 at 18:36
  • \$\begingroup\$ @jippie: onsemi.com/pub_link/Collateral/MC14517B-D.PDF \$\endgroup\$ – supercat Jul 28 '13 at 19:00
  • \$\begingroup\$ Sounds like each 64-bit shift register could be broken into 4 16-bit shift registers with the appropriate circuitry. \$\endgroup\$ – Ignacio Vazquez-Abrams Jul 28 '13 at 21:26
  • \$\begingroup\$ @IgnacioVazquez-Abrams: That would be a logical reason, but the way things are wired, I don't see how one could generally achieve that without the extra circuitry costing as much as simply using more smaller shifters [even without the mode pin, it's would be easy to regard the chip as two independent units, each of which can be hard-wired as an always-outputting 16, 32, 48, or 64-bit shifter]. \$\endgroup\$ – supercat Jul 28 '13 at 22:34
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The two most basic configurations for this circuit which I can think of are:

  1. Variable length shift register (middle taps are used as outputs)
  2. 64 bits serial memory element with x4 write speed (middle taps are used as inputs)

The above two are the most basic, and the middle taps are used for a single purpose in each of them. In 1, WE signal should not be asserted at all. In 2, the logic driving the middle taps should become a high impedance when WE gets deasserted.

We can find the application in which the middle taps will be used as both inputs and outputs: if you are using pins D, 16, 32 and 48 of both packaged registers (total of 8 pins) as inputs, and pins 16,32,48,64 of both packaged registers (total of 8 pins) as outputs - you get a 8-bits wide serial memory element. This memory can sample a Byte of data off the bus and put a Byte of data on the bus. If you are using a single bus for both reading and writing (which is usually the case), the fact that outputs go high Z when you assert WE is very handy - you can connect the bus directly to the inputs/outputs without any additional tri-states. Just make sure you are gating the clocks to both registers when you neither want to sample data off the bus, nor put the next sample on the bus.

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  • \$\begingroup\$ I suppose I could see a situation where the chip could be used if one wanted to be able to have an 8-bit bus read out the item that was written exactly 16 cycles before, but shifted over a bit, but that seems extremely obscure; I doubt if it comprises even 0.1% of the chip's applications. Further, that usage would work just fine if the chips had two mode pins, shared between both shift units, which could select one of four modes (two of which would behave like this chip actually does, along with e.g. 'shift while tristating everything' and 'shift while tristating all but last output'). \$\endgroup\$ – supercat Jul 28 '13 at 22:23
  • \$\begingroup\$ Normally, if one wanted to delay something by a multiple of the amount by which one shifter would delay, one would simply cascade shifters, but I see no practical way to do that if e.g. one wanted to use two chips to delay a bus by 32 cycles. The only way I can see to achieve a 32-cycle delay would be to use a toggle flop to count the number of operations, and some decode logic so that half the cycles would use one chip and half would use the other. \$\endgroup\$ – supercat Jul 28 '13 at 22:27
  • \$\begingroup\$ I appreciate your writing, and perhaps there is an intended usage is as a memory element, but the systems I've seen that would use bus-wired shift registers as memory elements include a means of recirculating data locally without putting it out on a shared bus. \$\endgroup\$ – supercat Jul 28 '13 at 22:52
  • \$\begingroup\$ @supercat, you wanted to know if there are applications where one can take advantage of both modes simultaneously - I described you such an application. I don't see a restriction on exactly 16 cycles delay, but I do see at least 16 cycles. I didn't understand what you said about impossibility of cascading - I see no such restriction. In general, this element will be used as variable length shift register (#1 in my answer). I don't know how do you estimate usage percentages, but I'm sure that variable length shift register is the major purpose of this chip. \$\endgroup\$ – Vasiliy Jul 29 '13 at 7:02
  • \$\begingroup\$ I would expect the normal usage would be as a fixed length register that's some multiple of 16 bits, but to use the chip for such purposes one would simply strap the WE pin (implying it may as well not exist). The reason for the "exact" 16 requirement with WE is that there is no way to get data from one 16-bit stage to another without having to output it on the bus. I guess my question could perhaps have been rephrased as "How often, if ever, has the 4017 actually been used in devices which ended up needing less circuitry than they would have if the WE pins had been internally strapped low?" \$\endgroup\$ – supercat Jul 29 '13 at 16:36

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