I have a simple Verilog module with only one synchronously reset DFF:
module scratch (input clk, reset_n, serial, output reg serial_ff); always @ (posedge clk) begin if (!reset_n) begin serial_ff <= 1'b0; end else begin serial_ff <= serial; end end endmodule // scratch
When running a lint check (hal 06.20-s004) on my design for ASIC, I get the following warning in the DFT category:
*W,FFWASR (./scratch.v,9|0): Flip-flop 'serial_ff' does not have any asynchronous set or reset. ------ Flip-flops must have asynchronous set or reset. If a flip-flop does not have any asynchronous set or reset then it is not controllable from primary inputs. The following example illustrates this problem: if(rst) port_a <= '0'; elsif rising_edge(clk) then port_a <= var_a; port_b <= var_b; end if; In the above HDL code, the value of 'port_a' can be brought to '0' using asynchronous reset 'rst', while this is not the case with 'port_b'. This may cause issues during simulation.
I am already using a synchronous reset for the FF, so it is getting initialized. But the warning tells me to use an asynchronous reset instead. But why is this important for testing? What sort of failures can this DFT methodology (asynchronous R instead of synchronous R) identify?
In short, when should I care, and when is it okay to ignore the warning?
Update: I found a parameter mentioned in passing in the documentation: "setreset_type". I grepped the entire doc set and it appears its undocumented. So I guess Cadence REALLY wants everyone to use async resets religiously. But the truth is that resets shouldn't be implemented religiously, but that the designer should consider the trade-offs and design requirements for any type of reset. This is the resounding conclusion of the answers so far, so you all get points for being helpful! I will update if I can find how to use that undocumented parameter. That was the only possible setting I could find after digging through all related documents. For now, I ignore the warning since we already have considered the design of the reset from the system architecture level.