# Quadrature counter on FPGA is running away

I am attempting to count pulses from a quadrature encoder in an Altera FPGA. I believe I have my counter set up correctly (circuit diagram below, following this tutorial), but when I turn my encoder on, the count just starts increasing non-stop. When I turn the encoder one way, the count speeds up, and when I turn it the other way it slows down, so it appears that I am in fact counting pulses, but also just counting up. Does anybody know why this might be?

simulate this circuit – Schematic created using CircuitLab

The count clock and count direction signals are going in to a 32-bit built-in counter function (LPM_COUNTER) on my Altera FPGA programmed using Quartus II v9.0. The output of this counter is stored in a buffer (LPM_BUSTRI) and read using a LabVIEW program whenever the LabVIEW code needs it. I have a similar LabVIEW code reading other buffers from the FPGA that is working fine, so I am fairly certain that the problem lies in my FPGA somewhere.

EDIT: Corrected the displayed clock frequency.

Make sure that the "clock count" signal is not being used as an actual clock into the counter. You want to use it as a "count enable". The clock into the counter should be the same 25.13 MHz clock that you used elsewhere.

Another issue worth keeping an eye on... When an encoder is not moving, sometimes it can get stuck in a sort of in between state. What you'll see is that either the A or B input could toggle back and forth somewhat quickly. In a properly designed system this shouldn't be an issue (you'll just see the count quickly change between two adjacent values). You might also see the equivalent of switch bounce on A and B as it changes value. Some quadrature encoders use mechanical switches, but even optical encoders could have something similar.

But this design requires that A and B do not change quickly. The inputs need to be at a constant value for 2 or 3 clocks before they are allowed to change. If this requirement is violated then it will not work correctly. I haven't done the work to figure out exactly how it will behave, but having it not count correctly is probable.

When I've done quadrature decoders, I've always done it more with a state machine than how you've done it here. Yours is fine, provided that you meet all the requirements, but there are better ways to do it.

• You, sir, are a genius! That seems to have helped, although I am still getting some run-away behavior. Now when I stop turning the encoder, sometimes the count stops, but sometimes it keeps running away like before. Any idea why this would intermittently be the case? – Engineero Jul 30 '13 at 17:48
• It looks pretty clean when I can measure it, but with the whole circuit connected it is possible I am getting some noise on the line. Do you think noise could cause the run-away I am seeing? I will try to get my scope back on there and see whether either phase is fluctuating when it should be still. – Engineero Jul 30 '13 at 17:54
• @Engineero I added some to my answer. – user3624 Jul 30 '13 at 17:59
• Thanks for the update. Do you have any references you could link on how to do it better with an FPGA like this? I have done it with a state machine on a National Instruments FPGA before, but I could not figure out how to get that scheme to work on my Altera board. Also, is there any other way that I can sort of filter my phases to prevent this type of run-away with the design I am using? – Engineero Jul 30 '13 at 18:03
• I will just make a separate question for the issue that I am still seeing. I would be interested to know what better ways there are of counting pulses that might be less prone to this run-away error, but your answer solved the immediate problem. Thank you! – Engineero Jul 31 '13 at 14:31