I am synthesizing some multiplication units in Verilog and I was wondering if you generally get better results in terms of area/power savings if you implement your own CSA using Booth Encoding when multplying or if you just use the * symbol and let the synthesis tool take care of the problem for you?
If your synthesis tools are any good then you should use the * operator, set reasonable constraints, and let the tools do the heavy lifting. This is particularly true for FPGAs, which may very fast and dense multiplier cells. The Xilinx Spartan-3 series, for example, has some very nice 9x9 multiplier cells. If you insist on writing logic equations for your own CSA multiplier the synthesizer may not be able to infer that you really want a multiplier, and the result would use lots of LUTs while the multiplier cells sit idle.
Let synthesis tool decide.
Unless you are interested in the intermediate results of multiplication, there will be no high gains in manual approach. In fact, given the very broad optimization strategies present in today's synthesis tools, the best you can manually get in terms of performance/area/power is the same (and there is good chance that your manual implementation will be worse).
The only scenario (in my opinion) when you won't let synthesis tool to take care of multiplication is when there are standard libs/modules for multipliers available (libs in ASICs, modules in FPGA). This approach is sometimes used in critical parts of the systems (critical in terms of performance/area/power). These cells are tailored for a particular usage (at layout level) and there is no chance that RLS will do better than that.
Unless you are setting some internal nodes of your Booth encoding multiplier as outputs, the synthesis tool will derive the low-level logic. Since the input and outputs of the two approaches are exactly the same, a good synthesis tool would optimize them in the exact same way, and the result would be no different. The only way you could force the synthesis tool to implement a booth multiplier is if you divided it into multiple blocks and disabled boundary optimization.