I would like to plane a PCB with mixed signals. I have the tms320f2809 with BGA footprint. I started to read some documentation "PCB Layout Recommendations for BGA Packages"

I got some question regarding the PCB design:

  • In mixed signal PCB the analog and digital ground has to be separated like the following image:

enter image description here

The tms320f2809 has a high speed ADC which requires an analog supply. Which layer and how should I route the analog sources(1V8,3V3) and grounds for the MCU ADC?

  • I can place the passive components on the 4th(bottom) layer. Can I place there the crystal oscillator as well?
  • \$\begingroup\$ DGND and AGND on the adc should be connected to the analog ground. Edit: assuming that the ADC is the only mixed signal device in your circuit \$\endgroup\$
    – crasic
    Aug 3, 2013 at 20:49
  • 1
    \$\begingroup\$ Analog devices has a very decent intro tutorial on grounding available here, crossing ground planes is bad, but the one on the right is only correct in certain situations, there are many other layout choices. Relevant to you are figures 5, 8, and 9 \$\endgroup\$
    – crasic
    Aug 3, 2013 at 20:54
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    \$\begingroup\$ your MCU acts as the star ground point for the Digital and Analog ground, you are basically only trying to restrict digital return currents from flowing back along the analog ground and coupling digital noise into the analog components, if your MCU is the only connecting point this condition is satisfied \$\endgroup\$
    – crasic
    Aug 3, 2013 at 20:57

4 Answers 4


In mixed signal PCB the analog and digital ground has to be separated like the following image:

That diagram looks like Figure 3 of the "partitioning and layout of a mixed signal pcb" article by Henry W. Ott in "printed circuit design" magazine (June 2001).

On the same page as that diagram, Ott says "Why do we need to split the ground plane ... ? The answer is we don't! Therefore, I prefer the approach of using only one ground plane and partitioning the PCB into digital and analog sections."

Later in the article Ott says "in almost all cases, both the functional performance and the EMC performance of the board will be better with the single ground plane [than with] split ground planes".

Use one solid unsplit ground plane under both the analog and the digital parts of the board.

Which layer and how should I route the analog sources(1V8,3V3) and grounds for the MCU ADC?

While many BGA parts only require 4 layers, it appears at first glance that this particular BGA package requires a minimum of 6 layers.

One common layer stackup for 6 layer boards is

1 signal
2 signal
3 power
4 ground
5 signal
6 signal

As shown the the documentation you already linked to: The ground plane is one solid unsplit ground plane -- with holes around vias just passing through, sold connections to GND vias, and thermal relief around GND through-holes. The power plane is chopped up into the various power supplies required for different regions of the board, with similar holes. (Sometimes it's better to route less-common power voltages on the signal layers of the board, rather than cut it out of the power plane).

on the ... bottom ... layer. Can I place there the crystal oscillator as well?

The vast majority of systems I've seen have all the components of a Pierce oscillator (the inverter, the crystal, two capacitors, and sometimes a series resistor) all on the same side of a PCB.

However, I have seen a system where the crystal was on the opposite side (Hamish Kellock OH2GAQ) and a paper that seems to recommend putting the two capacitors on the opposite side (Texas Instruments "PCB Design Guidelines For Reduced EMI").

So I'm pretty sure the oscillator will oscillate with the crystal on the opposite side from the inverter. As always, the EMI emitted (and the susceptibility of the oscillator to outside noise) is proportional to the loop area. Most of the time, it gets bigger (worse) if you put the crystal on the opposite side. (I don't know if your particular BGA package is one of the exceptions).


You are asking two separate questions here

  • Can I place passive components on the 4th layer and can I put the crystal there as well?

This will depend on your production capabilities as some build houses are not equipped to handle it. But, assuming the facility you use can. There are several advantages to having components on both sides of the PCB. It saves space and can allow you to place decoupling nearer to where you want it.

Typically I place a mixture of Surface mount components on the top of the board then flow solder, Next I place Surface mount components (SMT) on the bottom of the board glued in place. I try to limit these to 0805 size and larger and place them such that they are 90 degrees to the direction of travel over the wave to minimize soldering problems. Finally I place conventional pin through hole (PTH non-SMT) components on the top side of the board. The top side PTH and the bottom side SMT get soldered together at flow solder.

  • Secondly you asked about Ground and power planes.

Except in special circumstances we are not usually overly concerned about trying to maintain controlled impedances on tracks. What we are concerned with is minimising loop area. This is because a loop leads to inductance.

At high frequencies to minimise the energy in a signal (and hence the noise it can generate) the return current will want flow such as to minimise this area. One possibility is to individually consider each current loop and place the return 0V track directly underneath the signal track. The signal is therefore going out on the top of the board and returning on the bottom of the board directly underneath the outgoing signal.

You do see this on some boards; for example switch mode power supplies but for general digital circuits this becomes impractical as it rapidly becomes too difficult to understand all the return paths.

This is why we have ground planes: because if the the entire area is 0V then the return current will naturally find the optimum path.

The reason why crossing split ground planes is a bad idea is that you are forcing current to flow in a large loop as there is no direct path for the return current; it has to find an indirect path.

My personal preference would be to have the top layer signals trying to keep the analogue and digital signals as separate as possible. This may be easy if the only point where analogue meets digital is at an ADC. Depending on the amount of analogue circuitry we may have a single 0VD plane or the 0VA may be on a signal layer with the analogue and digital grounds being joined together at a single point near the ADC.

  • \$\begingroup\$ My only concern is the MCU(with ADC) which footprint is BGA, because of this it is hard to segregate the analog and digital signal. \$\endgroup\$
    – Mokus
    Aug 3, 2013 at 21:24

The grounds are not restricted to any layer. The components can be applied to either side. The crystal being in the parallel mode is high impedance and near zero current so is not a significant radiator but the CMOS input impedance being determined by a feedback resistor ~> 1M for the osc. design, will be somewhat sensitive to stray noise. Highspeed logic tracks between the Xtal and the ground plane are not allowed.

Stray noise coupling is effectively a few pF and depends on size. Gnd shielding acts as a capacitive shunt divider to stray noise.

The idea behind separate grounds is the minimize ground shift from transient spikes from high transition currents and reactive track impedance response. Analog ground noise must be null with respect to logic ground at the ADC and then spread out from there, where noise will rise from stray sources. Physical isolation forces current in separate paths to some extent and the A & D ground plane gap determines the capacitive coupling to each other which is small with a large gap.

The osc cap connect to CMOS out will conduct some current. Ic=C dV/dt e.g. = 10pF 3V/1nS=30mA peak and often limited with an internal or external resistor of 1K.

Connecting ground to other layers is best done with 3 or more microvias to reduce via inductance when high dI/dt currents are involved.


In mixed signal PCB the analog and digital ground has to be separated like the following image.

The left part of the image show the signal tracks crossing over the split planes, while the right part of the image shows the signal tracks avoiding the cross over the split planes. But important point is why should I avoid the signal tracks crossing over the split planes? As you check the stack up (cross section) of the PWB/PCB, some of the specific layers say TOP, INNER LAYER 1 only will support the controlled track impedance of say 50 ohms. This 50 ohm is achieved with respect to the layer below or above it acting as reference. And when you force a signal track or bunch of tracks to pass over the split planes, as show in left part of image, the part of the track which is above/below split will not be 50 ohms causing reflection and disturbing the integrity of the signal. Have a look at Page 8

Which layer and how should I route the analog sources(1V8,3V3) and grounds for the MCU ADC?

Make sure the 1.8V and 3.3V analog sources should be kept away from digital portion and power supply section of the board, and whatever layer you choose to route them, their should be proper ground reference to these supplies.

  • 1
    \$\begingroup\$ I think it's the high inductance, not the \$\ne 50 \Omega\$ characteristic impedance, of signal-lines-crossing-split-ground-planes that's the problem. \$\endgroup\$
    – Phil Frost
    Aug 3, 2013 at 20:19
  • \$\begingroup\$ Thank you rectifying me Phil, but I think its the characteristics impedance. Please have a look at the reference from Intel I added in the answer. \$\endgroup\$
    – AKR
    Aug 4, 2013 at 5:03

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