I have an combinational entity that is implemented with a lot of combinational logic. Synthesis (using Xilinx ISE) indicates:
Maximum combinational path delay: 62.367ns
When placed into a synchronous (clocked) design, the maximum frequency the entire system (clock domain) can operate at is only ~16 MHz. Essentially this one component would drive the entire system's maximum clock rate down.
What I want to do, is wrap this combinational component up in some synchronous logic (with
done output), that essentially "waits" on the propagation delay of the async component. Basically it just latches in the input, waits N clock cycles, and then latches the output to a register. However, after synthesis ISE still says
Maximum Frequency: 16.975MHz.
How do I get ISE to ignore the propagation delay of this device? Or, how else can I attack this?
I mean combinational instead of asynchronous.
This is part of a homework assignment. We previously were to implement a factorial module in each of "iterative", "low-latency" (combinational), and "high-throughput" (registered stages). Now we're using the first two of those in IP cores for Xilinx XPS system builder. The synchronous implementation was a piece of cake to get working (probably because that's how it should be done!) Of course, the timing constraints aren't met for the low-latency version, so I have to add logic to address this.
Now that I know the term is "Multicycle Path", the following resources are helpful: