I've developed some IP using Xilinx ISE, and this required settings some multi-cycle path constraints in the UCF file:
NET "lowlat_result<0>" TPTHRU = "through_lowlat_result"; # .... NET "clk" TNM_NET = clk; TIMESPEC TS_clk = PERIOD "clk" 125 MHz HIGH 50%; TIMESPEC TS_multipath_factll_result = FROM "FFS" THRU "through_lowlat_result" TO "FFS" TS_clk / 20;
I want to now utilize this VHDL code in a Xilinx Platform Studio (EDK 13.2) custom peripheral. There is no generated UCF file for the peripheral itself. Can I add one?
Or, do my constraints need to go in the main
data/system.ucf file? I'm not sure of how the scoping works for net names in entities many layers deep.