There are two register R1 and R2. How is it possible to exchange the content of R1 and R2 in a single clock pulse using Common bus architecture?

  • 1
    \$\begingroup\$ I don't know what "common bus architecture" is supposed to mean, but unless there is a instruction to exchange the contents of two registers, you probably can't do it in a single instruction cycle. \$\endgroup\$ – Olin Lathrop Aug 7 '13 at 17:30
  • \$\begingroup\$ Are you designing your own Hardware in an FPGA or are you interfacing to a MCU? \$\endgroup\$ – Nick Williams Aug 7 '13 at 18:15

You can't. CBA doesn't work that way.

  • \$\begingroup\$ I was studying Register transfer language from the book Morris Mano. It's clearly written there that it's possible(I have also studied this on a number of sites). See the following link slideshare.net/sanjeevpatel4x/register-transfer-language \$\endgroup\$ – Jatin Khurana Aug 20 '13 at 20:06
  • \$\begingroup\$ @JatinKhurana RTL is completely unrelated to CBA. You can't look at one and infer the capabilities of the other. \$\endgroup\$ – user3624 Aug 21 '13 at 14:48

Exchanging registers in a single cycle is only possible if both registers can present themselves as input to the other register at the same time. Only a single register can emit to the bus at any time, therefore a minimum of 3 cycles would be required (store R1, move R2 to R1, load R2; or the XOR trick, which still requires 3 operations).

  • \$\begingroup\$ With some pipeline configurations, effective two-cycle operation may be possible: during the first cycle, something on the bus may be stored to some register while register A outputs. During the second cycle, register B is output to the bus and loaded from it. During the third cycle, A is loaded from the bus while something else is output to it. Operations would be spread over three cycles, but the first and last could be shared with other operations. \$\endgroup\$ – supercat Aug 8 '13 at 3:19

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