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I am new to designing in and coding with with Altera Quartus II version 13 Web edition FPGA software. I am trying to split my design across serval blocks in order to make it more manageable.

How do I define an output from a gate in one Block/Schematic diagram (a .bdf file) so I can use it as an input on a gate in another Block/Schematic Diagram without making the output from the first diagram go to a pin first. Think of it as wire from one block to the next.

I do not want the output of the first block to be routed to a real pin.

Reading around got me something along "Node" and "Wire"

I am sure it is dead simple.

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closed as unclear what you're asking by Olin Lathrop, Leon Heller, placeholder, Anindo Ghosh, Dave Tweed Aug 11 '13 at 15:23

Please clarify your specific problem or add additional details to highlight exactly what you need. As it's currently written, it’s hard to tell exactly what you're asking. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

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    \$\begingroup\$ Huh? I don't see how anyone can help without even knowing the package you are using. Generally, if you want the system to know two things are connected, this is done in the schematic. \$\endgroup\$ – Olin Lathrop Aug 9 '13 at 14:56
  • \$\begingroup\$ I just did a quick Google and a BDF is a Block Design File which makes a bit more sense given the question. If that's what you mean you should edit the question to make it clearer. \$\endgroup\$ – PeterJ Aug 9 '13 at 15:12
  • \$\begingroup\$ @OlinLathrop Block design files are actually a way to visually design the digital logic, very much like normal schematics. It's just pure digital gate logic. \$\endgroup\$ – Benjamin Aug 9 '13 at 18:05
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  1. Make sure any nodes you'll want to access from another block are connected to input or output pins in the BDF
  2. You didn't say what version of Quartus you're using, but somewhere under the file menu, there will be a dialog along the lines of "Create block symbol file". This will run a compile, and generate a .bsf file of your current BDF.
  3. You can now add that BSF as a block in another BDF.

If this question doesn't get closed, I might come back and expand this answer to include some graphics.

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  • \$\begingroup\$ Regarding #1 Are you talking about a real pin on the FPGA here or just a virtual pin (if such exists) ? In the meantime I'll try and give #2 a shot. I also updated the question with the version info. \$\endgroup\$ – Benjamin Aug 9 '13 at 18:12
  • \$\begingroup\$ Input and output pins that you insert into the BDF. \$\endgroup\$ – Matt Young Aug 9 '13 at 22:52
  • \$\begingroup\$ Worked fantastic. \$\endgroup\$ – Benjamin Aug 10 '13 at 21:13

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