I am new to designing in and coding with with Altera Quartus II version 13 Web edition FPGA software. I am trying to split my design across serval blocks in order to make it more manageable.
How do I define an output from a gate in one Block/Schematic diagram (a .bdf file) so I can use it as an input on a gate in another Block/Schematic Diagram without making the output from the first diagram go to a pin first. Think of it as wire from one block to the next.
I do not want the output of the first block to be routed to a real pin.
Reading around got me something along "Node" and "Wire"
I am sure it is dead simple.