When writing Verilog, I use a variety of "linters" that will give errors and warnings. These are my simulator (ModelSim), my compiler (Quartus II), along with a linter (Verilator). Together, I have good coverage for common pitfalls, such as bus size mismatches and inferred latches.

Unfortunately, none of the three tools detects registers which are not being reset. To see what I mean, consider the following.

reg a;
reg b;

always @(posedge clk_i or posedge rst_i) begin
  if(rst_i) begin
    a <= 1'b0; // Reset a
    // Ooops, forgot to reset b
  end else begin
    // Do stuff with a and b

How can I have my tools automatically detect registers which are not being reset?

  • 2
    \$\begingroup\$ "registers which are not reset" are not necessarily a bad thing (at least in a silicon design), which may be why they are not warnings in lint tools. In general you only want to reset the registers that need to be reset, as adding resets to flip flops increases their area and the load on the reset network. If you have a 256-bit data bus and a one bit 'valid' signal, there's no need to reset the data if you reset the valid. \$\endgroup\$
    – Tim
    Commented Aug 9, 2013 at 17:13
  • \$\begingroup\$ Synplicity (synthesis tool) gives warnings about such things. Annoying because they are often intentional... but may help with your situation (assuming Synplicity does Verilog, I've never tried) \$\endgroup\$
    – user16324
    Commented Aug 9, 2013 at 19:54
  • \$\begingroup\$ The question states that a variety of linters are being used, ModelSim, Quartus II, and Verilator. These tools have limited linting capabilities, and the types of problems they check for are quite narrow. \$\endgroup\$ Commented Aug 20, 2013 at 9:33

4 Answers 4


None of the tools you mentioned is a real linting tool. These tools are not supposed to give you a good linting coverage.

I saw two commercial linting tools and both had rules for detecting non-reset flops.

I see three options:

  1. If the answer by David Kessner works for you - way to go.
  2. Get a decent linting tool which will do the job.
  3. Write a script which will detect non-reset flops.

Now, #2 may be not that simple. I don't know whether there are good free linters out there, and the professional ones are expensive and will take you a lot of time to setup.

#3 is the approach I would use. If you know any scripting language (Perl, Python, ...) it will take you one day at most to write a script which searches for non-reset flops. If you do not know any scripting language, there is StackOverflow where you can ask for a help - few days and you're done. This will also add another tool into your personal toolbox which is very valued among front-end designers - writing text processing scripts.

Good luck!


When I run Modelsim on my VHDL designs, it gives me warnings at Time=0ps about logic with 'X' or 'U' type input signals. I forget the exact warning message. Going through these warnings can tell me what I do not have initialized.


I rely on functional tests rather than linting tools for this, I tend to toggle reset and re-play parts of the test bench. If the device works correctly after reset, then you've either reset the state space sufficiently, or your test bench is no good!


Sometimes the design tools will output a series of reports that provide you with all sorts of interesting info. For example, Xilinx might call this a Map Report, which tells you what logical components were mapped to what physical components.

In the example above, reg a would be mapped to an FDCE (Flip flop, D, with asynchronous Clear, and clock Enable), while reg b would be mapped to an FDE (Flip flop, D, and clock Enable). This would tell you that reg b has no reset.


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