When writing Verilog, I use a variety of "linters" that will give errors and warnings. These are my simulator (ModelSim), my compiler (Quartus II), along with a linter (Verilator). Together, I have good coverage for common pitfalls, such as bus size mismatches and inferred latches.
Unfortunately, none of the three tools detects registers which are not being reset. To see what I mean, consider the following.
reg a; reg b; always @(posedge clk_i or posedge rst_i) begin if(rst_i) begin a <= 1'b0; // Reset a // Ooops, forgot to reset b end else begin // Do stuff with a and b end end
How can I have my tools automatically detect registers which are not being reset?