I've recently designed a FPGA breakout board using an FPGA BGA package, and due to the lack of packages I had on hand, I got the BGA-256 and drew new symbols and updated the connections from scratch.

Everything was spot on until I started drawing the schematic - upon a quick spot check to the PCB layout, my one BGA had turned into two identically-oriented packages with identical airwires as well as identical pin consolidation within the BGA array.

Any ideas on how to correct this issue? I cannot delete the duplicate part because if I do, I receive the "No forward-/backward-annotation can be performed!" error. Here's the schematic: enter image description here

Board with "cloned" device: enter image description here

So, what I was trying to do is put two pairs (four FPGAs) of FPGAs together for bitcoin mining onto a DIMM-form card that can "hot socket" into a multi-socket backplane/motherboard that carries the I/O and interface devices.

To save space and prevent from cluttering the schematic excessively, I decided to only connect pins that I determined were needed for my setup, namely the configuration and power pins and certain pins from I/O banks 0 to 3. Mapping these pins would also give me a much clearer view upon routing.

This is why the FPGA symbol in the schematic is multi-grouped and not a standard shape or size. The larger symbol to the left is a representation of the DIMM edge connector that I will build these FPGAs to. The only connection I have made at the point of screen capturing was to tie low all appropriate grounding points on the edge connector and FPGA ballout.

At first glance, because I stated I was using two pairs, having second copies may seem to make my life easier; but instead of having two pairs in parallel, I would have two doing the exact same thing.

  • \$\begingroup\$ Welcome to EE.SE. Please post your schematic and layout. I have a guess as to why you've got 2x ICs instead of one. Without the schematic it's hard to be sure. While you don't have enough reputation to post inline images, you can upload the photo to some 3rd party image hosting site (e.g. flicker, picasa, etc), then edit your post and add a link to that photo. Somebody with enough reputation will edit your post and inline the photo. Alternatively, you could upload the files somewhere on the web and add a link to your post (Eagle files or PDFs). \$\endgroup\$ Commented Aug 13, 2013 at 2:45
  • \$\begingroup\$ Alright, I just posted both the schematic and the board so you can also see the duplicated component. Read the edit; I'm in the process of writing a more detailed writeup as to what I was planning on doing with this. That, when connected with the way the board looks, will make more sense. Thanks for your help. \$\endgroup\$
    – ecfedele
    Commented Aug 13, 2013 at 4:41
  • \$\begingroup\$ I've just included the images, for the schematic it might be worth putting the devices closer together and doing a crop, images here only display as 630 x 424 pixels. \$\endgroup\$
    – PeterJ
    Commented Aug 13, 2013 at 4:45
  • \$\begingroup\$ I edited my post with a good amount of elaboration about the setup and its purpose, if anyone needs any more information run it past me and I'll provide you with whatever you need. \$\endgroup\$
    – ecfedele
    Commented Aug 13, 2013 at 4:49
  • \$\begingroup\$ IT is a common problem with PCB when you have multiple symbol components. Check out the references to all of your items, make sure you do not have the same pins assigned to 2 different symbols, that is one common problem. It is hard to see this on your schematic you attached. \$\endgroup\$
    – FarhadA
    Commented Aug 13, 2013 at 9:28

1 Answer 1


My hypothesis is that the FPGA in the schematic is drawn as multiple sub-components along the lines of U51A, U51B, U52C, etc. U52C was intended as U51C, that's the error. Even though there is only one sub-component of U52 present, Eagle adds the whole IC to the board.

** I've made up the designators U51 and U52. The images in the O.P. have low resolution, and the designators aren't readable. I'm guessing that slender vertical component on the left is the connector, and the group of components on the right is the FPGA split into multiple sub-components.

  • \$\begingroup\$ You have it pretty much spot-on - the components are marked U$1 and U$2, along the lines of the pretty-standard Eagle designators. The vertical component is the edge connector. That being said - do you think simply connecting the individual segments of the FPGA will resolve the issue? \$\endgroup\$
    – ecfedele
    Commented Aug 13, 2013 at 5:28
  • \$\begingroup\$ What are the designators of all of your FPGA sub-componets that you have? List them with all the -A's and -1's that there might be. Alternatively, zoom-in on the portion of the schematic, which has the FPGA, and post the screenshot. \$\endgroup\$ Commented Aug 13, 2013 at 5:36
  • \$\begingroup\$ Interesting thing just occurred - I originally did not have the blank ">NAME" designator on each of the sub-units. Upon adding them, it unified the device. A board check confirms there is only one BGA256 footprint. \$\endgroup\$
    – ecfedele
    Commented Aug 13, 2013 at 10:31

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