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I am trying to design layout, schematic and symbol, and then using symbol or schematic to test my design.

Here is the schematic:

enter image description here

And here is the layout I designed:

enter image description here When I run DRC, I get the following warnings, but I hope I can ignore those:

enter image description here Lastly, the simulation settings and output plot.

enter image description here As you see, I get 0 no matter what the input voltage is. Am I doing simulation wrong, is there any problem with my design?

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  • \$\begingroup\$ Links don't work! \$\endgroup\$ Aug 13, 2013 at 20:24
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    \$\begingroup\$ Why didn't you connect power supplies to the drain/source of your transistors? \$\endgroup\$
    – Renan
    Aug 13, 2013 at 20:28
  • \$\begingroup\$ I would double check your schematic - there is no path for current to flow to the output. \$\endgroup\$
    – dext0rb
    Aug 13, 2013 at 20:28
  • \$\begingroup\$ Besides, you first need to get the simulation working then do the physical layout. \$\endgroup\$
    – Renan
    Aug 13, 2013 at 20:29
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    \$\begingroup\$ Ignore most of the nonsense about the order that "this must be done in". the DRC is sufficiently decoupled that it shouldn't affect the simulations. Unless you've done an extraction and are simulating the as laid out cell for parasitics I'd not worry about it. You look to have a problem with the configuration of your simulation tool. This looks like Cadence Assura or some variant, so this may be harder to track down as the tool is overly configurable. As an aside, your layout should also include net labels for the LVS tool to run properly. \$\endgroup\$ Aug 13, 2013 at 21:13

2 Answers 2

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You forgot to connect several of the terminals in the schematic (the ones that have the yellow X marks over them). The PMOS source and back-gate need to be connected to a supply, and the NMOS source and back-gate need to be connected to ground.

Also, don't bother laying out the circuit until the simulation is working based on the schematic. You should be able to get the final layout DRC and LVS clean.

Edit: I'm not sure why it's not working with the new schematic. Did you set the supply voltage? (It's possible that the supply symbol isn't actually doing anything besides setting a net name.)

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  • \$\begingroup\$ I updated the schematic. Does the order matter? I created layout first then schematic. Even though if we skip drc errors, I think this should have worked with current sizing. \$\endgroup\$
    – www
    Aug 13, 2013 at 20:53
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You've connected a power net symbol (vdd!), but didn't connect a voltage source to that node.

Don't start layout until you at least have a working schematic.

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