-4
\$\begingroup\$

I am new to this FPGA. can any one help with the following :

Does Spartan 6 XC6SLX9 have an internal oscillator ?. If so what are its specifications ? , how can i access that ? . Please share any material, code available regarding the same.

\$\endgroup\$
  • 2
    \$\begingroup\$ Did you even search the web? \$\endgroup\$ – Mels Aug 14 '13 at 9:22
  • \$\begingroup\$ Welcome to EE SE by the way. Please read the How to Ask-page for instructions on how to ask an effective questions. \$\endgroup\$ – Mels Aug 14 '13 at 9:28
2
\$\begingroup\$

I believe Xilinx guide UG382 (Spartan-6 FPGA Clocking Resources User Guide) answers your question.

\$\endgroup\$
  • \$\begingroup\$ Actually, it does not, the relevant information on the internal ring oscillator is in UG380. \$\endgroup\$ – alex.forencich Aug 7 '15 at 1:05
2
\$\begingroup\$

Most FPGAs contain internal ring oscillators for managment purposes. Things like configuration loading on startup (where do you think clock for master SPI and master selectMAP comes from on Xilinx FPGAs?). In some cases, it is possible to access this oscillator. Looks like this is possible at least on the Virtex 6 and Spartan 6. On these devices, the oscillator is approximately 50 MHz +/- 50% (so 25-75 MHz, see http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-clock-source/td-p/437084). It will vary part-to-part and with voltage and temperature, though, so you can't rely on a very specific frequency. This can be used for utility logic such as transceiver reconfiguration and board bring-up logic such as static I2C writes to external clock management logic and PLLs.

For a Spartan 6, you need to instantiate the STARTUP_SPARTAN6 primitive and connect to the CFGMCLK port. See the configuration user guide, UG380. This is a direct tap off of the internal configuration ring oscillator. You'll have to tie off all of the inputs appropriately so everything works correctly. Looks like you need to tie EOS, GSR, and GTS low and KEYCLEARB high. Make sure to pass CFGMCLK through a BUFG before using it to drive logic, and make sure to constrain it to at least 75 MHz (13 ns) to make sure that frequency variations in the oscillator will still let your design meet timing.

This is also possible on the Virtex 6 with the STARTUP_VIRTEX6 primitive. Similar procedure, just different ports to tie off. It may be possible with other FPGAs.

\$\endgroup\$
0
\$\begingroup\$

There is no user-accessible internal oscillator (such as you might find on many microcontrollers) on Spartan 6 devices.

You can use a DCM as a free-running oscillator, but you need to "get-it-going" with some clock-like signal. See Figure 2-20 in the user guide: http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

\$\endgroup\$
  • \$\begingroup\$ Yes, there actually is. See UG380. \$\endgroup\$ – alex.forencich Aug 7 '15 at 1:06
  • \$\begingroup\$ I knew of the internal oscillator, but nothing I had read (at the time of writing the answer) gave any clue how to access said oscillator from within the FPGA logic, so I have assumed it was not feasible. I see from your answer that it is possible - thanks. \$\endgroup\$ – Martin Thompson Aug 7 '15 at 11:49

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.