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I'm trying to make a module with VHDL for my DE2 where the easy thing ("Hello World") is nearly impossible. The bakground is that I'm trying to run Hello World:

https://stackoverflow.com/questions/17966235/nios-2-hello-world/18267202?noredirect=1#18267202

http://www.cs.columbia.edu/~sedwards/classes/2013/4840/lab3.pdf

And now I'm following the instrution which are not working with my version of Quartus II v13: enter image description here

What does the error message mean? Am I doing something else wrong from what you can tell from the screenshots?

Info: *******************************************************************
Info: Running Quartus II 32-bit Generate HDL Interface
Info:     Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info:     Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info:     Your use of Altera Corporation's design tools, logic functions 
Info:     and other software and tools, and its AMPP partner logic 
Info:     functions, and any output files from any of the foregoing 
Info:     (including device programming or simulation files), and any 
Info:     associated documentation or information are expressly subject 
Info:     to the terms and conditions of the Altera Program License 
Info:     Subscription Agreement, Altera MegaCore Function License 
Info:     Agreement, or other applicable license agreement, including, 
Info:     without limitation, that your use is for the sole purpose of 
Info:     programming logic devices manufactured by Altera and sold by 
Info:     Altera or its authorized distributors.  Please refer to the 
Info:     applicable agreement for further details.
Info:     Processing started: Fri Aug 16 09:52:04 2013
Info: Command: quartus_map not_a_project --generate_hdl_interface=C:/Users/student/Desktop/KTH/colombia/de2_sram_controller.vhd --source=C:/Users/student/Desktop/KTH/colombia/de2_sram_controller.vhd --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/student/AppData/Local/Temp/alt5933_4160154550827554259.dir/0002_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on
Error: VHDL syntax error at de2_sram_controller.vhd(20) near text € File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 20
Error: VHDL syntax error at de2_sram_controller.vhd(20) near text "€";  expecting ";" File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 20
Error: VHDL syntax error at de2_sram_controller.vhd(20) near text ™ File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 20
Error: VHDL syntax error at de2_sram_controller.vhd(21) near text € File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 21
Error: VHDL syntax error at de2_sram_controller.vhd(21) near text ™ File: /users/student/desktop/kth/colombia/de2_sram_controller.vhd Line: 21
Warning: Quartus II 32-bit Generate HDL Interface was unsuccessful. 5 errors, 0 warnings
Error:     Peak virtual memory: 364 megabytes
Error:     Processing ended: Fri Aug 16 09:52:06 2013
Error:     Elapsed time: 00:00:02
Error:     Total CPU time (on all processors): 00:00:01
Error: No modules found when analyzing null.

Update

My VHDL compilation error is now this

Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Fri Aug 16 17:48:44 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lab3 -c lab3
Warning (20028): Parallel compilation is not licensed and has been disabled
Error (10500): VHDL syntax error at lab3.vhd(20) near text 
Error (10500): VHDL syntax error at lab3.vhd(20) near text "";  expecting ";"
Error (10500): VHDL syntax error at lab3.vhd(20) near text 
Error (10500): VHDL syntax error at lab3.vhd(21) near text 
Error (10500): VHDL syntax error at lab3.vhd(21) near text 
Info (12021): Found 0 design units, including 0 entities, in source file lab3.vhd
Error (10430): VHDL Primary Unit Declaration error at de2_sram_controller.vhd(3): primary unit "de2_sram_controller" already exists in library "work"
Error (10784): HDL error at lab3.vhd(3): see declaration for object "de2_sram_controller"
Error (10500): VHDL syntax error at de2_sram_controller.vhd(22) near text 
Error (10500): VHDL syntax error at de2_sram_controller.vhd(22) near text "";  expecting ";"
Error (10500): VHDL syntax error at de2_sram_controller.vhd(22) near text 
Error (10500): VHDL syntax error at de2_sram_controller.vhd(23) near text 
Error (10500): VHDL syntax error at de2_sram_controller.vhd(23) near text 
Info (12021): Found 0 design units, including 0 entities, in source file de2_sram_controller.vhd
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 12 errors, 1 warning
    Error: Peak virtual memory: 476 megabytes
    Error: Processing ended: Fri Aug 16 17:48:45 2013
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 14 errors, 1 warning

The code is

library ieee;
use ieee.std_logic_1164.all;
entity de2_sram_controller is
port (
signal chipselect : in std_logic;
signal write, read : in std_logic;
signal address : in std_logic_vector(17 downto 0);
signal readdata : out std_logic_vector(15 downto 0);
signal writedata : in std_logic_vector(15 downto 0);
signal byteenable : in std_logic_vector(1 downto 0);
signal SRAM_DQ : inout std_logic_vector(15 downto 0);
signal SRAM_ADDR : out std_logic_vector(17 downto 0);
signal SRAM_UB_N, SRAM_LB_N : out std_logic;
signal SRAM_WE_N, SRAM_CE_N : out std_logic;
signal SRAM_OE_N : out std_logic
);
end de2_sram_controller;

architecture dp of de2_sram_controller is
begin

    SRAM_DQ <= writedata when write = ’1’
                    else (others => ’Z’);
    readdata <= SRAM_DQ;
    SRAM_ADDR <= address;
    SRAM_UB_N <= not byteenable(1);
    SRAM_LB_N <= not byteenable(0);
    SRAM_WE_N <= not write;
    SRAM_CE_N <= not chipselect;
    SRAM_OE_N <= not read;

end dp;
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  • 4
    \$\begingroup\$ Considering the odd characters in the errors I wonder if some 'invisible junk' has come across when you've pasted from the PDF. Maybe take a look at de2_sram_controller.vhd using a few different text editors or a hex editor and see if you can spot anything odd. \$\endgroup\$ – PeterJ Aug 16 '13 at 8:27
  • \$\begingroup\$ @PeterJ Yes, I could fix the error but I immediately got a new error. can you help me fix it? I pasted the code and the compilation error as an update to the question. \$\endgroup\$ – Niklas Rosencrantz Aug 16 '13 at 15:50
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    \$\begingroup\$ I've never done much with VHDL (just basing this on similar problems with other compilers) but the problems seem to appear around the extra break after the begin - maybe it doesn't like the line breaks - it could be a platform CR/LF handling type thing. Maybe try deleting that blank line and see how it goes, or perhaps even delete a few lines either side and just type them back in. \$\endgroup\$ – PeterJ Aug 16 '13 at 16:03
  • \$\begingroup\$ @PeterJ It seems the line that the compiler is complaining about is SRAM_DQ <= writedata when write = ’1’ but I can't see what is wrong with that, I copied it from the insctruction document. I suppose I must investigate more. \$\endgroup\$ – Niklas Rosencrantz Aug 16 '13 at 16:06
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    \$\begingroup\$ Didn't spot that but I've also had problems with unusual quote characters, I'm not sure of the proper name for the ones above but try regular single quotes typed from your keyboard ('). The above is probably a Unicode character. \$\endgroup\$ – PeterJ Aug 16 '13 at 16:09
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Your code is okay, I managed to compile it with ghdl. But only after I replaced the backticks. Here's how it looks in hex:

$ hd -s 0x2ee -n 7 test.vhd.orig 
000002ee  e2 80 99 5a e2 80 99                              |...Z...|

The compiler won't accept that as '. You said you've replaced them in the comments, but obviously something went wrong. Just delete the whole line and type it by hand. You learn a lot more anyway, if you don't just copy and paste..

I tried all ways to write ' and that might not even be the problem since it appears that the compiler is complaining about the row where it says begin

The line number the compiler tells you, isn't always where you've made a mistake. Just take it as a hint. For example if you forget a ; the compiler usually indicates the error where the next statement begins.

A good debugging strategy for obscure errors is to remove lines until your code compiles. That helps to find the exact location and works especially well with VHDL (compared to other programming languages).

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