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The 3rd and 4th column in the image below (from wikipedia) says "enhancement, no bulk". What does "no bulk" mean?

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  • \$\begingroup\$ I think a slightly better question is "What is Bulk in Mosfets?". \$\endgroup\$ – Passerby Aug 17 '13 at 14:53
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One has to be careful when you are dealing with Wikipedia as evidenced by even the symbols you show above. While there are no "standards" that are commonly accepted, each design group usually adopts their own symbols, there is some meaning to the elements of the symbols. In particular the dotted line for the channel shows enhancement (i.e. the channel is "broken" before use. Depletion mode devices have a solid line because the channel exists before power is applied. The symbols above do NOT apply this rule evenly ...

There are a certain class of device that actually do not have bulk connections. They are called FD-SOI CMOS (Fully depleted - Silicon On Insulator). They are characterized by a layer of Si that is so thin that the depletion layer from the channel formation extends throughout it's depth. The bulk/Body connection goes away but the bulk/body is still there when the device is turned off. But the effect of it's non-connection is minimized (although noticeable in the transistor characteristics).

In every other case the bulk connection is there but is not shown simply as a shorthand way to draw quickly or to have less cluttered diagrams. Usually in that case it is understood what the bulk connection should be.

In the case of individual FETs (like Power Fets and HexFets) the bulk is connected to the source in package to minimize the number of leads. This can be done simply because the each die does reside as an individual die. When you have multiple transistors on the same substrate that is electrically connected one must always show the bulk in detailed designs.

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They mean that the "Bulk" electrode is omitted from the symbol of the transistor.

This approach simplifies the symbols, but might be used only when there is no ambiguity as to the potential of the bulk. I know of two conventions where these symbols come quite handy (and simplify the schematics):

  1. Bulks of all the transistors are connected to the same potential.
  2. Bulks of all the transistors are internally connected to transistors' sources.

The first approach is usually adopted in VLSI - all the transistors are implemented on the same layer of silicon, and the potential of this layer is common for all of them.

I heard that the second approach is usually adopted in vertical power FETs.

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  • \$\begingroup\$ -1, It should be a -1/2 though but I can't vote that way. Your VLSI comment only applies to simplified sketches. All modern VLSI processes are on P-type wafers, this forces all the NMOS to have the same bulk connection (unless you have a triple well process). The PMOS bulk/Well connections MUST always be shown and connected , the tools will not allow you to leave those unconnected. So your statement is wrong and your reasoning for that is wrong for PMOS, the NWell to Substrate connection provides junction isolation for the PMOS from device to device (unless they are in the same well). \$\endgroup\$ – placeholder Aug 17 '13 at 15:23
  • \$\begingroup\$ Also, I'd say the internal bulk-source connection (usually called body, not bulk for discrete transistors) is nearly universally adopted for all MOSFETs, not just vertical power FETs. In fact, I have only encountered one device with separate bulk/source connections: CD4007UB. \$\endgroup\$ – Phil Frost Aug 17 '13 at 15:29
  • \$\begingroup\$ MOSFET: Why the drain and source are different? \$\endgroup\$ – Phil Frost Aug 17 '13 at 15:33
  • \$\begingroup\$ @rawbrawb, if you want to teach someone, you must consider what amount of information to provide. The statement I made is not correct for NMOS either because there are always some local and global potential gradients in the Bulk. This is the reason you have these p+ diffusions connected to ground spread throughout the chip (even without triple well) - you want to make sure that the Bulk's potential does not vary too much. However, this information is irrelevant to the question, and I believe OP won't understand neither your -1, nor my reply. \$\endgroup\$ – Vasiliy Aug 17 '13 at 15:39
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    \$\begingroup\$ The point of this site is a Q and A format to act as a repository for the OP as well as future enquires. Factual accuracy is important. The OP MAY not understand my comment, but YOU should and future visitors should see it for accuracy. Modern processes are on EPI substrates, the NWells are nailed tight. \$\endgroup\$ – placeholder Aug 17 '13 at 15:48

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