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We are designing an image processing pipeline on an FPGA which will need the use of memory interfaces at various pipeline stages. Because of the size of the memory required we decided to go with a DDR3 design.

It would be really useful if the pipeline stages can access there own memory in an independent manner so that I can minimize arbitration. I was thus hoping to implement multiple "narrow" DDR3 modules (16 bit wide for instance) each with it's own controller on the FPGA so that the stages' memory interfaces can be completely separate.

My other option is using multiple DDR3 modules in a single rank with one controller.

Does anybody have any experience in using multiple controllers on an FPGA? Or would the single controller be the safer bet?

We will be using a mid range Kintex for the implementation.

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  • \$\begingroup\$ Ask your Xilinx FAE. \$\endgroup\$ – user3624 Aug 18 '13 at 21:00
  • \$\begingroup\$ I don't have experience with that particular implementation, but my assumption would be that, as long as you have available cells, and available interconnect, and available pins, you can have multiple parallel controllers, and that would actually be preferrable for the reasons you suggest (less arbitration, well-defined throughput at each stage.) \$\endgroup\$ – Jon Watte Aug 18 '13 at 22:42
  • \$\begingroup\$ I want to ask one related question. Kintex series FPGA has a 1 dedicated pin set for only one ddr-3 memory controller. so does it mean I could connect only One set (one chip select) ddr-3 memory to the Kintex? \$\endgroup\$ – user30831 Oct 24 '13 at 5:59
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Does anybody have any experience in using multiple controllers on an FPGA?

Yes, I've helped out on a design for an HD video pipeline that used two DDR memory controllers, but I don't know whether they were DDR3 specifically. One 32-bit wide memory held the main frame buffer, and the other 16-bit wide memory held overlay information. Worked quite well.

Or would the single controller be the safer bet?

That's really a separate question altogether. Depending on the bandwidth requirements of the different "users" of this memory, the overall recurring system cost can be lower if you can funnel everything through a single memory controller and a single set of memory chips. But the design time and risks (NRE costs) will be higher. I have also taken this approach on a different (SD) project.

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As long as you have sufficient logic cells and IO pins, you can have as many memory interfaces as you like.

On the downside, narrow memory implies soldering chips down rather than using DIMMs (or other modules) which means a significant cost premium - unless you are buying huge volumes of chips.

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