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In the Quartus II settings (under TimeQuest timing analyser), I have checked the Report worst-case paths during compilation checkbox.

However, I do not see any worst-case paths in the TimeQuest report. How can I generate timing worst-case paths in Quartus II version 12.1? Is there a way to manually generate the worst-case paths report?

The target FPGA is a Stratix V. It seems that when the target FPGA is a Cyclone IV, all works fine, but not for the Stratix V.

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  • \$\begingroup\$ does your design meet the timing or not? You can go to TimeQuest, there you select failing report, select failing path clock, if you right-click there you can choose the number of failing path. \$\endgroup\$ – FarhadA Aug 20 '13 at 4:19
  • \$\begingroup\$ @FarhadA: It's not meeting timing by a bit. \$\endgroup\$ – Randomblue Aug 27 '13 at 14:00
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It's non-obvious how to use the QuartusII built in reports. You need to start from the page Multicorner Timing Analysis Summary and look down the right hand side looking for any setup, hold, recovery or removal slacks that are negative. Once you find the failing clock and type of failure (setup, hold) you can hunt around for the details in other sections. As a guide: setup/recovery failures are (usually) found in the slow/hot model, and hold/removal failures are uncovered when testing at the fast/cold corner.

Generally I ignore the reports built into Quartus and do timing analysis in the seperate TimeQuest Timing Analyser GUI. Launch it from Quartus by double clicking TimeQuest Timing Analyzer under Timequest Timing Anaysis in the Quartus "Task" view or by hitting the stopwatch on the toolbar.

There are many ways to drive this tool. One way is to list all the design clocks by double clicking Reports -> Slack -> Report Setup Summary, then right click on the clock of interest and choose Report Timing.... The clock section is pre-filled out and ignore the other fields, so just hit the "Report Timing" button. You will get a Summary of Paths screen showing the most critical slacks by path. From here you can chase through to either Chip Planner for routed view, or back to RTL/Technology viewer to look at source. Note the most critical model is selected depending on the report type.

If you have any non-zero counts on the Unconstrained Paths section the tools will complain. It takes a few hours to go through and properly constrain board signals but worth cleaning it up.

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You can also run this TCL command to spit out a report instead of using the GUI (also works on Quartus Prime):

report_timing \
    -setup \
    -npaths 2000 \
    -detail full_path \
    -panel_name {Report Timing} \
    -multi_corner \
    -file "worst_case_paths.rpt"

You may have to run the following first:

create_timing_netlist -model slow
read_sdc
update_timing_netlist
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