I want to define a parameter in Verilog in such a way that several modules will be able to use it.

Each module is implemented in different file.

Can it be done or should I (re)define this parameter in each module ?


If you want to share a parameter among a limited set of modules within your ovarall design, you can define the parameter in an enclosing module, and then pass it into the modules that need it using the following instantiation syntax:

parameter PARAM = value;

module_name #(.PARAM(PARAM)) instance_name ( ... );

Each of the lower-level modules must also declare the parameter, and they can optionally give it a default value as well (which will be overridden by the value passed in during instatiation).

  • \$\begingroup\$ I prefer to have top level blocks pass parameters down to children explicitly as @dave_tweed suggests, rather than `include files. Preprocessor based solutions sometimes give problems with tool/simulator flows later. \$\endgroup\$ – shuckc Aug 29 '13 at 10:07

How about putting the parameter into a separate file, and then `include this file into any files that want to have the parameter defined? That gives you single point of update in case you want to change the value later.

I'm assuming you don't just want it to be global, or else you can just use `define.


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