VHDL don't care for integer

Question

I am writing a reset for a vhdl statemachine that has an integer signal, which is initialized in the second state of the statemachine. However for completeness (assign every signal to avoid latches) I would like to assign a don't care value to the signal, so the synthesis tool has the most room for optimization.

Is there any way to assign a don't care value to a signal of the type integer? (I know I could convert it to signed/unsigned and assign (others => '-' ) however it feels more natural to write this code with integer, since this allows to write if var=3 ... instead of if to_integer(var)=3 ... or if var=to_(un)signed(3, var'Length)... which feels uncomfortable.

Of I can not assign don't care, what is the best practice, assign the value, that I will assign in the second state, leave it unassigned or others? (I would go with assigning the value from the second state early)

Answer 1

There is no "don't care" for integer; if you are modelling digital logic with X, Z, don't care etc, then numeric_std.signed/unsigned is the right way to go.

But look at the numeric_std package more carefully; most operators including = are overloaded with forms that allow mixing [un]signed and integer freely, so that if my_unsigned_var = 3 just works...