Accessing RAM instance from multiple modules in Verilog

Question

I am trying to make a single instance of RAM module accessible in different modules without instantiating it in every module. Since If I instantiate RAM module in each module, there are two more copies of it, taking up twice or more as much Block RAM as needed. There is no concern about modules trying to access it in the same time, as they run one after the other. How can I do it?

P.S. providing memory as input to each module seems like incorrect solution..

Answer 1

If you're trying to model how actual hardware would do it, you should:

1. Define an interface with the necessary ports (read/write, address, write data, return data)
2. Add these ports to any unit which wishes to access the ram.
3. Create an arbitration module which connects to all the other modules with ram interface ports, and let this module arbitrate the requests of all the different modules, access the physical ram, and return the read data to the module which requested it.

If you're just doing this for simulation and you don't care about synthesis, then you can just use a hierarchical reference to a ram block somewhere (simtop.u_ram.wr_data = 0x123). But I think writing it in a synthesizable way as described above is the most clean and logical way to do it.