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I have a Verilog submodule which I am testing independently. This module has too many top level pins to fit in my FPGA, so I have set some of the pins as virtual so that it would compile without optimizing away the corresponding signals.

I am however concerned that the timing analysis is affected by setting those pins as virtual. I have a feeling that the pins are effectively false pathed.

Does setting top level pins as virtual in Quartus II affect timing? If so, how can I make sure that the timing analysis is as if the FPGA had enough pins to start with?

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I just finished a project at the customer site mapping an IP with over 2700 IOs. In the first steps the project, we used a wrapper to put all the signals into a giant shift register to make sure they were not optimized. But later on we used the Virtual IOs to get the timing of the design correct and get the right estimate of the needed resources for the project.

Using Virtual IO, in my experience does not affect the timing of your design. You can "FALSE PATH" those signals if you want, but if you don't and those signals are connected to one of your clocks, then you will get the proper timing analysis of those signals.

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You need to create another module inside your FPGA that connects to all of those signals, and also has connections to real pins on your FPGA. Something like a long shift register — think JTAG chain. This will force the synthesis tools to treat all of those signals as real and apply the correct timing constraints to them.

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    \$\begingroup\$ It is no longer necessary. In Quartus, you can use Virtual IO and in Vivado you can set the "out of context" setting to synthesis and immplement your IP without the need to create a wrapper or the whole design. This helps IP designers to get a good estimate of the needed resources as well as optimizing the timing of their IP. \$\endgroup\$ – FarhadA Aug 23 '13 at 8:59
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Virtual pins are placed as feeding the input LUT in a free ALM, which can be placed very close to your design logic. Timing to the assigned LUT will be checked as usual, including any combinatorial outputs your block has on that path. This is what you want when inspecting the complexity of the block, although during integration the actual destination could be much further away.

If you look at ChipPlanner you will find the submodule densely packed in the centre using virtual IO pins. If you route to physical pins, assuming there's enough, you will find the design stretched out like a spiders web as the fitter tries to meet timing (and most likely cannot). Since most of the IO will probably come through buses from dedicated hard PCS blocks from HSSI pads in IP cores, there's no point in fitting it to hard pins.

Update: What you might like to try is adding a design partition for your block, and setting up a logic lock region for that partition which is a small subsection of the whole chip. This will give you a little square of area that the core will have to meet timing within, with an unlimited number of interconnections coming out on the periphery. This will then give you timing analysis on the input/outputs to a strict boundary, which may be more realistic than arbitrary/favourably positioned Virtual pins LUTs.

Quartus help: def_virtual_pin

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    \$\begingroup\$ Are you sure that the virtual IOs have FalsePath associated with them? \$\endgroup\$ – FarhadA Aug 22 '13 at 17:47
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    \$\begingroup\$ Revising my answer. \$\endgroup\$ – shuckc Aug 23 '13 at 9:49
  • \$\begingroup\$ Just a quick note, you do not need to create a bloc in order to use Virtual IO with Quartus, you can let the P&R some freedom in the early stages of the IP development rather than focusing on making a block out of it. \$\endgroup\$ – FarhadA Aug 23 '13 at 9:51

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