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I am using synplify, and wrote a utility library for my project, that contains the following function:

function truncate(x: in std_logic_vector; constant length: in integer)
return std_logic_vector is
    variable result : std_logic_vector(length-1 downto 0);
begin
    result := x(length-1 downto 0);
    return result;
end function;

However Synplify gives the following error (line 197 is the one where I declare the result variable):

@E:CD866 : utility.vhd(197) | Expression is not a constant(static) expression

My questions are:

  • Why do I get the error? (I thought in synthesis the function is inlined and everything is fine)
  • How can I work arround it? (I tried marking the length as const, but that did not work, besides it will screw up the later part.)
  • If the workarround is: just write it out, can i formulate result <= a(a'left downto a'right+cut) & truncate(unsigned(b)+2, cut); without using additional immediates? (I know that result <= a(a'left downto a'right+cut) & (b+2)(cut-1 downto 0); won't work without calculating cut-1 in an intermediate vector and then using a subset of that vector.)

Important NOTE:

My design contains a part were I combine two vectors somewhat similar to this (cutis an input signal, thus not constant):

result <= a(a'left downto a'right+cut) & truncate(b, cut);

While I have a feeling that this might be the source of the problem, I do not see why such a contraption should not be synthesizable (after all it is just several multiplexers and cut controls which ones take "bits" from a/brespectivley.

(The reason is i find truncate(x, y) more readable than x(y-1 downto 0), furthermore one could extend this function to work regardless of range direction and offest (e.g. a vector x only defined for a range k downto l where l>0.

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Note that your return value has a dynamic length. In synthesis, this implies a physical bus that has a varying number of bits, which most certainly is not synthesizable. Try padding the return value with zeros so that it can have a constant width...that shouldn't make any difference to the later AND operation.

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  • \$\begingroup\$ I see where you come from. So far I tried using the & operator to concat and not the bitwise and. I guess I will just write a function for the messy part that introduces a temp signal as mentioned in my editied question. \$\endgroup\$ – ted Aug 22 '13 at 11:11

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