I have a design (Memoryintefacing module) with two processes as proposed by gaisler, one combinatorial process and one clocked to operate the registers. The whole entity generates a ready signal, which blocks the entities communiting with it. To not block them prematurely write access only generate a blocking signal if the entity is already busy processing a read or write. To allow for this the first state latches the supplied address and data, so a later write request won't overwrite the address half way through the process.
The problem I encounter in simulation is the following, in two consecutive cycles I request writes with different addresses. The first write starts fine, we are in the
INITIAL state, the address is driven on the addressbus and the data and address are latched. The simulation of this clocks rising edge finishes and we go on to the next. Now the process for the statemachine is executed first. It sees the new address and latches the new address and drives it. Directly thereafter the register process triggers and updates the statemachines state. In the following delta cycle the statemachine jumps to the correct state not updating the latched data or the address driven. However my address driven and the latched value are screwed up already.
Is there any technic to achieve correct simulation results without a simulation considering register timing? Does my design still contain a major flaw (should I update my latch only at the clock edge in the register process)?